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verilog [2009/03/28 09:42] (current)
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 +
 +<code verilog>
 +
 +module adderDebug (
 +    a,
 +    b,
 +    c
 +);
 +
 +input [7:0] a;
 +input [7:0] b;
 +output [8:0] c;
 +reg [8:0] c;
 +
 +
 +
 +always @(a or b) begin: _adderDebug
 +    
 +    c <= (a + b);
 +end
 +
 +endmodule
 +module adderRef (
 +    a,
 +    b,
 +    c
 +);
 +
 +input [7:0] a;
 +input [7:0] b;
 +output [8:0] c;
 +reg [8:0] c;
 +
 +
 +
 +always @(a or b) begin: _adderRef
 +    c <= (a + b);
 +end
 +
 +endmodule
 +module augmOps (
 +    Bitand,
 +    Bitor,
 +    Bitxor,
 +    FloorDiv,
 +    LeftShift,
 +    Mod,
 +    Mul,
 +    RightShift,
 +    Sub,
 +    Sum,
 +    left,
 +    right
 +);
 +
 +output [7:0] Bitand;
 +reg [7:0] Bitand;
 +output [7:0] Bitor;
 +reg [7:0] Bitor;
 +output [7:0] Bitxor;
 +reg [7:0] Bitxor;
 +output [7:0] FloorDiv;
 +reg [7:0] FloorDiv;
 +output [63:0] LeftShift;
 +reg [63:0] LeftShift;
 +output [7:0] Mod;
 +reg [7:0] Mod;
 +output [14:0] Mul;
 +reg [14:0] Mul;
 +output [7:0] RightShift;
 +reg [7:0] RightShift;
 +output [7:0] Sub;
 +reg [7:0] Sub;
 +output [8:0] Sum;
 +reg [8:0] Sum;
 +input [7:0] left;
 +input [6:0] right;
 +
 +
 +
 +always @(left or right) begin: _augmOps
 +    reg [64-1:0] var;
 +    var = left;
 +    var = var & right;
 +    Bitand <= var;
 +    var = left;
 +    var = var | right;
 +    Bitor <= var;
 +    var = left;
 +    var = var ^ left;
 +    Bitxor <= var;
 +    if ((right != 0)) begin
 +        var = left;
 +        var = var / right;
 +        FloorDiv <= var;
 +    end
 +    if (((left < 256) && (right < 40))) begin
 +        var = left;
 +        var = var << right;
 +        LeftShift <= var;
 +    end
 +    if ((right != 0)) begin
 +        var = left;
 +        var = var % right;
 +        Mod <= var;
 +    end
 +    var = left;
 +    var = var * right;
 +    Mul <= var;
 +    var = left;
 +    var = var >> right;
 +    RightShift <= var;
 +    if ((left >= right)) begin
 +        var = left;
 +        var = var - right;
 +        Sub <= var;
 +    end
 +    var = left;
 +    var = var + right;
 +    Sum <= var;
 +end
 +
 +endmodule
 +module behRef (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +initial begin: _behRef
 +    integer i;
 +    integer j;
 +    while (1) begin
 +        if ((reset == 0)) begin
 +            @ (posedge reset);
 +        end
 +        for (i=0; i<20; i=i+1) begin
 +            @ (posedge clock);
 +            if (enable) begin
 +                count <= i;
 +            end
 +        end
 +        j = 1;
 +        while ((j < 25)) begin
 +            if (enable) begin
 +                @ (posedge clock);
 +            end
 +            @ (posedge clock);
 +            count <= (2 * j);
 +            j = j + 1;
 +        end
 +    end
 +end
 +
 +endmodule
 +module bin2gray2 (
 +    B,
 +    G
 +);
 +
 +input [7:0] B;
 +output [7:0] G;
 +reg [7:0] G;
 +
 +
 +
 +always @(B) begin: _bin2gray2
 +    integer i;
 +    reg [9-1:0] Bext;
 +    Bext = 9'h0;
 +    Bext = B;
 +    for (i=0; i<8; i=i+1) begin
 +        G[i] <= (Bext[(i + 1)] ^ Bext[i]);
 +    end
 +end
 +
 +endmodule
 +module bin2gray (
 +    B,
 +    G
 +);
 +
 +input [7:0] B;
 +output [7:0] G;
 +reg [7:0] G;
 +
 +
 +
 +always @(B) begin: _bin2gray
 +    integer i;
 +    reg [9-1:0] Bext;
 +    Bext = B;
 +    for (i=0; i<8; i=i+1) begin
 +        G[i] <= (Bext[(i + 1)] ^ Bext[i]);
 +    end
 +end
 +
 +endmodule
 +module binaryOps (
 +    Bitand,
 +    Bitor,
 +    Bitxor,
 +    FloorDiv,
 +    LeftShift,
 +    Mod,
 +    Mul,
 +    Pow,
 +    RightShift,
 +    Sub,
 +    Sum,
 +    EQ,
 +    NE,
 +    LT,
 +    GT,
 +    LE,
 +    GE,
 +    And,
 +    Or,
 +    left,
 +    right
 +);
 +
 +output [7:0] Bitand;
 +reg [7:0] Bitand;
 +output [7:0] Bitor;
 +reg [7:0] Bitor;
 +output [7:0] Bitxor;
 +reg [7:0] Bitxor;
 +output [7:0] FloorDiv;
 +reg [7:0] FloorDiv;
 +output [63:0] LeftShift;
 +reg [63:0] LeftShift;
 +output [7:0] Mod;
 +reg [7:0] Mod;
 +output [14:0] Mul;
 +reg [14:0] Mul;
 +output [63:0] Pow;
 +reg [63:0] Pow;
 +output [7:0] RightShift;
 +reg [7:0] RightShift;
 +output [7:0] Sub;
 +reg [7:0] Sub;
 +output [8:0] Sum;
 +reg [8:0] Sum;
 +output EQ;
 +reg EQ;
 +output NE;
 +reg NE;
 +output LT;
 +reg LT;
 +output GT;
 +reg GT;
 +output LE;
 +reg LE;
 +output GE;
 +reg GE;
 +output And;
 +reg And;
 +output Or;
 +reg Or;
 +input [7:0] left;
 +input [6:0] right;
 +
 +
 +
 +always @(left or right) begin: _binaryOps
 +    Bitand <= (left & right);
 +    Bitor <= (left | right);
 +    Bitxor <= (left ^ right);
 +    if ((right != 0)) begin
 +        FloorDiv <= (left / right);
 +    end
 +    if (((left < 256) && (right < 40))) begin
 +        LeftShift <= (left << right);
 +    end
 +    if ((right != 0)) begin
 +        Mod <= (left % right);
 +    end
 +    Mul <= (left * right);
 +    Pow <= 0;
 +    RightShift <= (left >> right);
 +    if ((left >= right)) begin
 +        Sub <= (left - right);
 +    end
 +    Sum <= (left + right);
 +    EQ <= (left == right);
 +    NE <= (left != right);
 +    LT <= (left < right);
 +    GT <= (left > right);
 +    LE <= (left <= right);
 +    GE <= (left >= right);
 +    And <= ((left && right) ? 1'b1 : 1'b0);
 +    Or <= ((left || right) ? 1'b1 : 1'b0);
 +end
 +
 +endmodule
 +module ConstWire2 (
 +    p,
 +    q
 +);
 +
 +input p;
 +output q;
 +reg q;
 +
 +wire s;
 +reg r;
 +wire _inst1_r;
 +
 +
 +assign s = 1;
 +assign _inst1_r = 0;
 +initial begin: _ConstWire2_inst1_gen_or
 +    while (1) begin
 +        r <= (p | _inst1_r);
 +        @ (p or _inst1_r);
 +    end
 +end
 +
 +initial begin: _ConstWire2_inst2
 +    while (1) begin
 +        q <= (r | s);
 +        @ (r or s);
 +    end
 +end
 +
 +endmodule
 +module ConstWire3 (
 +    p,
 +    q
 +);
 +
 +input [7:0] p;
 +output [7:0] q;
 +reg [7:0] q;
 +
 +wire [4:0] t;
 +
 +
 +assign t = 17;
 +always @(p or t) begin: _ConstWire3_adder_inst
 +    q <= (p + t);
 +end
 +
 +endmodule
 +module decRef (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output signed [7:0] count;
 +reg signed [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +always @(posedge clock or negedge reset) begin: _decRef
 +    if ((reset == 0)) begin
 +        count <= 0;
 +    end
 +    else begin
 +        if (enable) begin
 +            if ((count == (-128))) begin
 +                count <= (128 - 1);
 +            end
 +            else begin
 +                count <= (count - 1);
 +            end
 +        end
 +    end
 +end
 +
 +endmodule
 +module decTaskFreeVar (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output signed [7:0] count;
 +reg signed [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +task _MYHDL668_decTaskFunc;
 +begin: _MYHDL669_RETURN
 +    if (enable) begin
 +        if ((count == (-128))) begin
 +            count <= (128 - 1);
 +        end
 +        else begin
 +            count <= (count - 1);
 +        end
 +    end
 +end
 +endtask
 +
 +always @(posedge clock or negedge reset) begin: _decTaskFreeVar
 +    if ((reset == 0)) begin
 +        count <= 0;
 +    end
 +    else begin
 +        _MYHDL668_decTaskFunc;
 +    end
 +end
 +
 +endmodule
 +module dec (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output signed [7:0] count;
 +reg signed [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +always @(posedge clock or negedge reset) begin: _dec
 +    if ((reset == 0)) begin
 +        count <= 0;
 +    end
 +    else begin
 +        if (enable) begin
 +            if ((count == (-128))) begin
 +                count <= (128 - 1);
 +            end
 +            else begin
 +                count <= (count - 1);
 +            end
 +        end
 +    end
 +end
 +
 +endmodule
 +module design1 (
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +input a;
 +input b;
 +input c;
 +input d;
 +output p;
 +wire p;
 +input [7:0] q;
 +input r;
 +
 +
 +
 +
 +assign p = (a | b);
 +
 +endmodule
 +module design2 (
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +input a;
 +input b;
 +input c;
 +input d;
 +output p;
 +wire p;
 +output [7:0] q;
 +wire [7:0] q;
 +output r;
 +wire r;
 +
 +
 +
 +
 +assign p = (a | b);
 +assign q = (c & d);
 +assign r = (a ^ c);
 +
 +endmodule
 +module design3 (
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +input a;
 +input b;
 +input c;
 +input d;
 +output p;
 +reg p;
 +output [7:0] q;
 +reg [7:0] q;
 +output r;
 +reg r;
 +
 +
 +
 +always @(a, c, b, d) begin: _design3
 +    if (a) begin
 +        p <= (c | b);
 +        q <= (c & d);
 +        r <= (d ^ c);
 +    end
 +end
 +
 +endmodule
 +module design4 (
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +input a;
 +input b;
 +input c;
 +input d;
 +output p;
 +reg p;
 +output [7:0] q;
 +reg [7:0] q;
 +output r;
 +reg r;
 +
 +
 +
 +always @(a, c, b, d) begin: _design4
 +    p <= (a | b);
 +    q <= (c & d);
 +    r <= (a ^ c);
 +    q <= (c | d);
 +end
 +
 +endmodule
 +module design5 (
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +input a;
 +input b;
 +input c;
 +input d;
 +output p;
 +reg p;
 +output [7:0] q;
 +reg [7:0] q;
 +output r;
 +reg r;
 +
 +
 +
 +always @(a, c, b, d) begin: _design5
 +    p <= (a | b);
 +    q <= (c & d);
 +    r <= (a ^ c);
 +    q[0] <= (c | d);
 +end
 +
 +endmodule
 +module ForBreakContinueLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForBreakContinueLoop
 +    integer i;
 +    out <= 0;
 +    begin: _MYHDL148_BREAK
 +    for (i=16-1; i>=0; i=i-1) begin: _MYHDL149_LOOP
 +        if ((a[i] == 0)) begin
 +            disable _MYHDL149_LOOP;
 +        end
 +        out <= i;
 +        disable _MYHDL148_BREAK;
 +    end
 +    end
 +end
 +
 +endmodule
 +module ForBreakLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForBreakLoop
 +    integer i;
 +    out <= 0;
 +    begin: _MYHDL153_BREAK
 +    for (i=16-1; i>=0; i=i-1) begin
 +        if ((a[i] == 1)) begin
 +            out <= i;
 +            disable _MYHDL153_BREAK;
 +        end
 +    end
 +    end
 +end
 +
 +endmodule
 +module ForContinueLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForContinueLoop
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=16-1; i>=0; i=i-1) begin: _MYHDL159_LOOP
 +        if ((a[i] == 0)) begin
 +            disable _MYHDL159_LOOP;
 +        end
 +        var = var + 1;
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module ForLoop1 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForLoop1
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=16-1; i>=0; i=i-1) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module ForLoop2 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForLoop2
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=16-1; i>=5; i=i-1) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module ForLoop3 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForLoop3
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=16-1; i>=3; i=i-2) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module ForLoop4 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForLoop4
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=0; i<16; i=i+1) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module ForLoop5 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForLoop5
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=6; i<16; i=i+1) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module ForLoop6 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _ForLoop6
 +    integer var;
 +    integer i;
 +    var = 0;
 +    for (i=5; i<16; i=i+3) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +    end
 +    out <= var;
 +
 +
 +
 +
 +end
 +
 +endmodule
 +module FramerCtrl_alt (
 +    SOF,
 +    state,
 +    syncFlag,
 +    clk,
 +    reset_n
 +);
 +
 +output SOF;
 +reg SOF;
 +output [2:0] state;
 +reg [2:0] state;
 +input syncFlag;
 +input clk;
 +input reset_n;
 +
 +
 +
 +always @(posedge clk or negedge reset_n) begin: _FramerCtrl_alt_FSM_1
 +    reg [3-1:0] state_var;
 +    reg [8-1:0] index;
 +    integer SOF_var;
 +    if ((reset_n == 0)) begin
 +        SOF <= 0;
 +        index = 0;
 +        state_var = 3'b001;
 +        state <= 3'b001;
 +    end
 +    else begin
 +        SOF_var = 0;
 +        // synthesis parallel_case full_case
 +        casez (state)
 +            3'b??1: begin
 +                index = 0;
 +                if (syncFlag) begin
 +                    state_var = 3'b010;
 +                end
 +            end
 +            3'b?1?: begin
 +                if ((index == 0)) begin
 +                    if (syncFlag) begin
 +                        state_var = 3'b100;
 +                    end
 +                    else begin
 +                        state_var = 3'b001;
 +                    end
 +                end
 +            end
 +            3'b1??: begin
 +                if ((index == 0)) begin
 +                    if ((!syncFlag)) begin
 +                        state_var = 3'b001;
 +                    end
 +                end
 +                SOF_var = (index == (8 - 1));
 +            end
 +            default: begin
 +                $display("ValueError(Undefined state)");
 +                $finish;
 +            end
 +        endcase
 +        index = ((index + 1) % 8);
 +        SOF <= SOF_var;
 +        state <= state_var;
 +    end
 +end
 +
 +endmodule
 +module FramerCtrl_ref (
 +    SOF,
 +    state,
 +    syncFlag,
 +    clk,
 +    reset_n
 +);
 +
 +output SOF;
 +reg SOF;
 +output [2:0] state;
 +reg [2:0] state;
 +input syncFlag;
 +input clk;
 +input reset_n;
 +
 +reg [7:0] index;
 +
 +
 +always @(posedge clk or negedge reset_n) begin: _FramerCtrl_ref_FSM_1
 +    if ((reset_n == 0)) begin
 +        SOF <= 0;
 +        index <= 0;
 +        state <= 3'b001;
 +    end
 +    else begin
 +        index <= ((index + 1) % 8);
 +        SOF <= 0;
 +        // synthesis parallel_case full_case
 +        casez (state)
 +            3'b??1: begin
 +                index <= 1;
 +                if (syncFlag) begin
 +                    state <= 3'b010;
 +                end
 +            end
 +            3'b?1?: begin
 +                if ((index == 0)) begin
 +                    if (syncFlag) begin
 +                        state <= 3'b100;
 +                    end
 +                    else begin
 +                        state <= 3'b001;
 +                    end
 +                end
 +            end
 +            3'b1??: begin
 +                if ((index == 0)) begin
 +                    if ((!syncFlag)) begin
 +                        state <= 3'b001;
 +                    end
 +                end
 +                SOF <= (index == (8 - 1));
 +            end
 +            default: begin
 +                $display("ValueError(Undefined state)");
 +                $finish;
 +            end
 +        endcase
 +    end
 +end
 +
 +endmodule
 +module FramerCtrl (
 +    SOF,
 +    state,
 +    syncFlag,
 +    clk,
 +    reset_n
 +);
 +
 +output SOF;
 +reg SOF;
 +output [2:0] state;
 +reg [2:0] state;
 +input syncFlag;
 +input clk;
 +input reset_n;
 +
 +
 +
 +always @(posedge clk or negedge reset_n) begin: _FramerCtrl
 +    reg [3-1:0] index;
 +    if ((reset_n == 0)) begin
 +        SOF <= 0;
 +        index = 0;
 +        state <= 3'b001;
 +    end
 +    else begin
 +        SOF <= 0;
 +        // synthesis parallel_case full_case
 +        casez (state)
 +            3'b??1: begin
 +                index = 0;
 +                if (syncFlag) begin
 +                    state <= 3'b010;
 +                end
 +            end
 +            3'b?1?: begin
 +                if ((index == 0)) begin
 +                    if (syncFlag) begin
 +                        state <= 3'b100;
 +                    end
 +                    else begin
 +                        state <= 3'b001;
 +                    end
 +                end
 +            end
 +
 +            3'b1??: begin
 +                if ((index == 0)) begin
 +                    if ((!syncFlag)) begin
 +                        state <= 3'b001;
 +                    end
 +                end
 +                SOF <= (index == (8 - 1));
 +            end
 +            default: begin
 +                $display("ValueError(Undefined state)");
 +
 +                $finish;
 +            end
 +        endcase
 +        index = ((index + 1) % 8);
 +    end
 +end
 +
 +endmodule
 +module FunctionCall (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +function integer _MYHDL193_ReturnFromFunction;
 +    input [16-1:0] a;
 +    integer i;
 +begin: _MYHDL196_RETURN
 +    for (i=16-1; i>=0; i=i-1) begin
 +        if ((a[i] == 1)) begin
 +            _MYHDL193_ReturnFromFunction = i;
 +            disable _MYHDL196_RETURN;
 +        end
 +    end
 +    _MYHDL193_ReturnFromFunction = 0;
 +    disable _MYHDL196_RETURN;
 +end
 +endfunction
 +
 +always @(a) begin: _FunctionCall
 +    out <= _MYHDL193_ReturnFromFunction(a);
 +end
 +
 +endmodule
 +module GrayIncReg (
 +    graycnt,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] graycnt;
 +reg [7:0] graycnt;
 +input enable;
 +input clock;
 +input reset;
 +
 +reg [7:0] graycnt_comb;
 +reg [7:0] _GRAY_INC_1_bincnt;
 +
 +
 +always @(posedge clock or negedge reset) begin: _GrayIncReg_GRAY_INC_1_INC_1
 +    if ((reset == 0)) begin
 +        _GRAY_INC_1_bincnt <= 0;
 +    end
 +    else begin
 +        if (enable) begin
 +            _GRAY_INC_1_bincnt <= ((_GRAY_INC_1_bincnt + 1) % 256);
 +        end
 +    end
 +end
 +
 +always @(_GRAY_INC_1_bincnt) begin: _GrayIncReg_GRAY_INC_1_BIN2GRAY_1
 +    integer i;
 +    reg [9-1:0] Bext;
 +    Bext = _GRAY_INC_1_bincnt;
 +    for (i=0; i<8; i=i+1) begin
 +        graycnt_comb[i] <= (Bext[(i + 1)] ^ Bext[i]);
 +    end
 +end
 +
 +always @(posedge clock) begin: _GrayIncReg_REG_1
 +    graycnt <= graycnt_comb;
 +end
 +
 +endmodule
 +module HecCalculatorFunc (
 +    hec,
 +    header
 +);
 +
 +output [7:0] hec;
 +reg [7:0] hec;
 +input [31:0] header;
 +
 +
 +
 +function [8-1:0] _MYHDL122_calculateHecFunc;
 +    input [32-1:0] header;
 +    integer i;
 +    reg [8-1:0] h;
 +    reg bit;
 +begin: _MYHDL125_RETURN
 +    h = 8'h0;
 +    for (i=32-1; i>=0; i=i-1) begin
 +        bit = header[i];
 +        h = {h[7-1:2], (bit ^ h[1] ^ h[7]), (bit ^ h[0] ^ h[7]), (bit ^ h[7])};
 +    end
 +    h = h ^ 85;
 +    _MYHDL122_calculateHecFunc = h;
 +    disable _MYHDL125_RETURN;
 +end
 +endfunction
 +
 +always @(header) begin: _HecCalculatorFunc
 +    reg [8-1:0] h;
 +    hec <= _MYHDL122_calculateHecFunc(header);
 +end
 +
 +endmodule
 +module HecCalculatorPlain (
 +    hec,
 +    header
 +);
 +
 +output [7:0] hec;
 +reg [7:0] hec;
 +input [31:0] header;
 +
 +
 +
 +always @(header) begin: _HecCalculatorPlain
 +    integer i;
 +    reg [8-1:0] h;
 +    reg bit;
 +    h = 0;
 +    for (i=32-1; i>=0; i=i-1) begin
 +        bit = header[i];
 +        h = {h[7-1:2], (bit ^ h[1] ^ h[7]), (bit ^ h[0] ^ h[7]), (bit ^ h[7])};
 +    end
 +    hec <= (h ^ 85);
 +end
 +
 +endmodule
 +
 +module HecCalculatorTask2 (
 +    hec,
 +    header
 +);
 +
 +output [7:0] hec;
 +reg [7:0] hec;
 +input [31:0] header;
 +
 +
 +
 +task _MYHDL141_calculateHecTask;
 +    input [32-1:0] header;
 +    output [8-1:0] hec;
 +    integer i;
 +    reg [8-1:0] h;
 +    reg bit;
 +begin: _MYHDL144_RETURN
 +    h = 8'h0;
 +    for (i=32-1; i>=0; i=i-1) begin
 +        bit = header[i];
 +        h = {h[7-1:2], (bit ^ h[1] ^ h[7]), (bit ^ h[0] ^ h[7]), (bit ^ h[7])};
 +    end
 +    h = h ^ 85;
 +    hec = h;
 +end
 +endtask
 +
 +always @(header) begin: _HecCalculatorTask2
 +    reg [8-1:0] h;
 +    _MYHDL141_calculateHecTask(header, h);
 +    hec <= h;
 +end
 +
 +endmodule
 +module HecCalculatorTask (
 +    hec,
 +    header
 +);
 +
 +output [7:0] hec;
 +reg [7:0] hec;
 +input [31:0] header;
 +
 +
 +
 +task _MYHDL134_calculateHecTask;
 +    output [8-1:0] hec;
 +    input [32-1:0] header;
 +    integer i;
 +    reg [8-1:0] h;
 +    reg bit;
 +begin: _MYHDL137_RETURN
 +    h = 8'h0;
 +    for (i=32-1; i>=0; i=i-1) begin
 +        bit = header[i];
 +        h = {h[7-1:2], (bit ^ h[1] ^ h[7]), (bit ^ h[0] ^ h[7]), (bit ^ h[7])};
 +    end
 +    h = h ^ 85;
 +    hec = h;
 +end
 +endtask
 +
 +always @(header) begin: _HecCalculatorTask
 +    reg [8-1:0] h;
 +    _MYHDL134_calculateHecTask(h, header);
 +    hec <= h;
 +end
 +
 +endmodule
 +module incRef (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +
 +always @(posedge clock or negedge reset) begin: _incRef
 +    if ((reset == 0)) begin
 +        count <= 0;
 +    end
 +    else begin
 +        if (enable) begin
 +            count <= ((count + 1) % 256);
 +        end
 +    end
 +end
 +
 +endmodule
 +module incTaskFreeVar (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +task _MYHDL23_incTaskFunc;
 +begin: _MYHDL24_RETURN
 +    if (enable) begin
 +        count <= ((count + 1) % 256);
 +    end
 +end
 +endtask
 +
 +always @(posedge clock or negedge reset) begin: _incTaskFreeVar
 +    if ((reset == 0)) begin
 +        count <= 0;
 +    end
 +    else begin
 +        _MYHDL23_incTaskFunc;
 +    end
 +end
 +
 +endmodule
 +module incTask (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +task _MYHDL18_incTaskFunc;
 +    inout [8-1:0] cnt;
 +    input [1-1:0] enable;
 +    input [1-1:0] reset;
 +    input n;
 +    integer n;
 +begin: _MYHDL19_RETURN
 +    if (enable) begin
 +        cnt = ((cnt + 1) % n);
 +    end
 +end
 +endtask
 +
 +always @(posedge clock or negedge reset) begin: _incTask
 +    reg [8-1:0] cnt;
 +    if ((reset == 0)) begin
 +        cnt = 0;
 +        count <= 0;
 +    end
 +    else begin
 +        _MYHDL18_incTaskFunc(cnt, enable, reset, 256);
 +        count <= cnt;
 +    end
 +end
 +
 +
 +endmodule
 +module inc (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +always @(posedge clock or negedge reset) begin: _inc
 +    if ((reset == 0)) begin
 +        count <= 0;
 +    end
 +    else begin
 +        if (enable) begin
 +            count <= ((count + 1) % 256);
 +        end
 +    end
 +end
 +
 +endmodule
 +module Infer1 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _Infer1
 +    integer c;
 +    c = 5;
 +    c = (a < 4);
 +    c = (0 ? 1'b1 : 1'b0);
 +    c = 1'b0;
 +    c = (!a);
 +    c = 1'b1;
 +    out <= c;
 +end
 +
 +endmodule
 +module Infer2 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _Infer2
 +    integer c;
 +    c = (a < 4);
 +    c = (0 ? 1'b1 : 1'b0);
 +    c = 1'b0;
 +    c = (!a);
 +    c = 1'b1;
 +    c = 5;
 +    out <= c;
 +end
 +
 +endmodule
 +module Infer3 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +function integer _MYHDL270_Infer3Func;
 +    input [16-1:0] a;
 +begin: _MYHDL271_RETURN
 +    if (1'b1) begin
 +        _MYHDL270_Infer3Func = (a > 0);
 +        disable _MYHDL271_RETURN;
 +    end
 +    else begin
 +        _MYHDL270_Infer3Func = 5;
 +        disable _MYHDL271_RETURN;
 +    end
 +end
 +endfunction
 +
 +always @(a) begin: _Infer3
 +    out <= _MYHDL270_Infer3Func(a);
 +end
 +
 +endmodule
 +module Infer4 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +function integer _MYHDL275_Infer4Func;
 +    input [16-1:0] a;
 +begin: _MYHDL278_RETURN
 +    while (1) begin
 +        if (1'b1) begin
 +            _MYHDL275_Infer4Func = 6;
 +            disable _MYHDL278_RETURN;
 +        end
 +        else begin
 +            _MYHDL275_Infer4Func = (a < 3);
 +            disable _MYHDL278_RETURN;
 +        end
 +    end
 +end
 +endfunction
 +
 +always @(a) begin: _Infer4
 +    out <= _MYHDL275_Infer4Func(a);
 +end
 +
 +endmodule
 +module Infer5 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _Infer5
 +    integer c;
 +    c = (a + 1);
 +    c = (a - 1);
 +    c = (a * 3);
 +    c = (a / 2);
 +    c = (a << 2);
 +    c = (a >> 2);
 +    c = (a % 16);
 +    c = (+a);
 +    c = (-(-a));
 +    c = (~(-3));
 +    c = (!a);
 +    c = (5 & 4);
 +    c = (5 | 2);
 +    c = (6 ^ 3);
 +    c = ((a && 1) ? 1'b1 : 1'b0);
 +    out <= c;
 +end
 +
 +endmodule
 +module InferError7 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +function [5-1:0] _MYHDL247_InferError7Func;
 +    input [16-1:0] a;
 +begin: _MYHDL248_RETURN
 +    if (a) begin
 +        _MYHDL247_InferError7Func = 5'h0;
 +        disable _MYHDL248_RETURN;
 +    end
 +    else begin
 +        _MYHDL247_InferError7Func = 5'h1f;
 +        disable _MYHDL248_RETURN;
 +    end
 +end
 +endfunction
 +
 +initial begin: _InferError7
 +    @ (a);
 +    out <= _MYHDL247_InferError7Func(a);
 +end
 +
 +endmodule
 +module listElementNotUnique (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +reg [7:0] mem [0:8-1];
 +
 +module multiOps (
 +    Bitand,
 +    Bitor,
 +    Bitxor,
 +    And,
 +    Or,
 +    argm,
 +    argn,
 +    argp
 +);
 +
 +output [6:0] Bitand;
 +reg [6:0] Bitand;
 +output [6:0] Bitor;
 +reg [6:0] Bitor;
 +output [6:0] Bitxor;
 +reg [6:0] Bitxor;
 +output And;
 +reg And;
 +output Or;
 +reg Or;
 +input [2:0] argm;
 +input [6:0] argn;
 +input [3:0] argp;
 +
 +
 +
 +always @(argm or argn or argp) begin: _multiOps
 +    Bitand <= (argm & argn & argp);
 +    Bitor <= (argm | argn | argp);
 +    Bitxor <= (argm ^ argn ^ argp);
 +    And <= ((argm && argn && argp) ? 1'b1 : 1'b0);
 +    Or <= ((argm && argn && argp) ? 1'b1 : 1'b0);
 +end
 +
 +endmodule
 +module my_bundle (
 +    p,
 +    q
 +);
 +
 +input p;
 +output q;
 +reg q;
 +
 +wire r;
 +
 +
 +
 +assign r = 0;
 +initial begin: _my_bundle_gen_or
 +    while (1) begin
 +        q <= (p | r);
 +        @ (p or r);
 +    end
 +end
 +
 +endmodule
 +module NestedForLoop1 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _NestedForLoop1
 +    integer var;
 +
 +    integer i;
 +    integer j;
 +    var = 0;
 +    begin: _MYHDL200_BREAK
 +    for (i=16-1; i>=0; i=i-1) begin: _MYHDL201_LOOP
 +        if ((a[i] == 0)) begin
 +            disable _MYHDL201_LOOP;
 +        end
 +        else begin
 +            for (j=i-1; j>=0; j=j-1) begin
 +                if ((a[j] == 0)) begin
 +                    var = var + 1;
 +                end
 +            end
 +            disable _MYHDL200_BREAK;
 +        end
 +    end
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module NestedForLoop2 (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _NestedForLoop2
 +    integer var;
 +    integer i;
 +    integer j;
 +    var = 0;
 +    out <= 0;
 +    begin: _MYHDL207_BREAK
 +    for (i=16-1; i>=0; i=i-1) begin: _MYHDL208_LOOP
 +        if ((a[i] == 0)) begin
 +            disable _MYHDL208_LOOP;
 +        end
 +        else begin
 +            begin: _MYHDL209_BREAK
 +            for (j=(i - 1)-1; j>=0; j=j-1) begin
 +                if ((a[j] == 0)) begin
 +                    // pass
 +                end
 +                else begin
 +                    out <= j;
 +                    disable _MYHDL209_BREAK;
 +                end
 +            end
 +            end
 +
 +
 +            disable _MYHDL207_BREAK;
 +        end
 +    end
 +    end
 +end
 +
 +endmodule
 +module ram2 (
 +    dout,
 +    din,
 +    addr,
 +    we,
 +    clk
 +);
 +
 +output [7:0] dout;
 +
 +reg [7:0] dout;
 +input [7:0] din;
 +input [7:0] addr;
 +input we;
 +input clk;
 +
 +
 +reg [7:0] memL [0:128-1];
 +
 +always @(posedge clk) begin: _ram2_WL
 +    if (we) begin
 +        memL[addr] <= din;
 +    end
 +end
 +
 +always @(posedge clk) begin: _ram2_RL
 +    dout <= memL[addr];
 +end
 +
 +endmodule
 +module ram3 (
 +    dout,
 +    din,
 +    addr,
 +    we,
 +    clk
 +);
 +
 +output [7:0] dout;
 +wire [7:0] dout;
 +input [7:0] din;
 +input [7:0] addr;
 +input we;
 +input clk;
 +
 +reg [7:0] read_addr;
 +
 +reg [7:0] memL [0:128-1];
 +
 +always @(posedge clk) begin: _ram3_WL
 +    if (we) begin
 +        memL[addr] <= din;
 +    end
 +    read_addr <= addr;
 +end
 +
 +
 +assign dout = memL[read_addr];
 +
 +endmodule
 +module ram (
 +    dout,
 +    din,
 +    addr,
 +    we,
 +    clk
 +);
 +
 +output [7:0] dout;
 +reg [7:0] dout;
 +input [7:0] din;
 +input [7:0] addr;
 +input we;
 +input clk;
 +
 +
 +
 +always @(posedge clk) begin: _ram
 +    reg [8-1:0] mem [0:128-1];
 +    reg [8-1:0] a;
 +    integer ad;
 +    if (we) begin
 +        ad = addr;
 +        mem[addr] = din;
 +    end
 +    dout <= mem[addr];
 +end
 +
 +endmodule
 +module RandomScrambler (
 +    o7,
 +    o6,
 +    o5,
 +    o4,
 +    o3,
 +    o2,
 +    o1,
 +    o0,
 +    i7,
 +    i6,
 +    i5,
 +    i4,
 +    i3,
 +    i2,
 +    i1,
 +
 +    i0
 +);
 +
 +output o7;
 +reg o7;
 +output o6;
 +reg o6;
 +output o5;
 +reg o5;
 +output o4;
 +reg o4;
 +output o3;
 +reg o3;
 +output o2;
 +reg o2;
 +output o1;
 +reg o1;
 +output o0;
 +reg o0;
 +input i7;
 +input i6;
 +input i5;
 +input i4;
 +input i3;
 +input i2;
 +input i1;
 +input i0;
 +
 +reg \_rs_i2[7]_a ;
 +reg \_rs_i2[7]_c ;
 +reg \_rs_i2[7]_b ;
 +reg \_rs_i2[6]_a ;
 +reg \_rs_i2[5]_a ;
 +
 +reg \_rs_i2[5]_c ;
 +reg \_rs_i2[4]_a ;
 +reg \_rs_i2[2]_c ;
 +reg \_rs_rs_i2[7]_a ;
 +reg \_rs_rs_i2[7]_c ;
 +reg \_rs_rs_i2[7]_b ;
 +reg \_rs_rs_i2[6]_a ;
 +reg \_rs_rs_i2[6]_c ;
 +reg \_rs_rs_i2[6]_b ;
 +reg \_rs_rs_i2[5]_a ;
 +reg \_rs_rs_i2[5]_c ;
 +reg \_rs_rs_rs_i2[7]_a ;
 +reg \_rs_rs_rs_i2[7]_c ;
 +reg \_rs_rs_rs_i2[7]_b ;
 +reg \_rs_rs_rs_i2[6]_c ;
 +reg \_rs_rs_rs_i2[6]_b ;
 +reg \_rs_rs_rs_i2[5]_a ;
 +reg \_rs_rs_rs_i2[5]_c ;
 +reg \_rs_rs_rs_i2[3]_a ;
 +reg \_rs_rs_rs_rs_i2[7]_a ;
 +reg \_rs_rs_rs_rs_i2[7]_c ;
 +reg \_rs_rs_rs_rs_i2[7]_b ;
 +reg \_rs_rs_rs_rs_i2[6]_a ;
 +reg \_rs_rs_rs_rs_i2[6]_c ;
 +reg \_rs_rs_rs_rs_i2[5]_a ;
 +reg \_rs_rs_rs_rs_i2[4]_c ;
 +reg \_rs_rs_rs_rs_i2[4]_b ;
 +reg \_rs_rs_rs_rs_rs_i2[7]_a ;
 +reg \_rs_rs_rs_rs_rs_i2[7]_c ;
 +reg \_rs_rs_rs_rs_rs_i2[7]_b ;
 +reg \_rs_rs_rs_rs_rs_i2[6]_a ;
 +reg \_rs_rs_rs_rs_rs_i2[6]_c ;
 +reg \_rs_rs_rs_rs_rs_i2[5]_a ;
 +reg \_rs_rs_rs_rs_rs_i2[4]_c ;
 +reg \_rs_rs_rs_rs_rs_i2[1]_a ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[7]_a ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[7]_c ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[7]_b ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[6]_a ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[6]_c ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[5]_b ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[4]_c ;
 +reg \_rs_rs_rs_rs_rs_i1_i1[1]_a ;
 +reg _rs_rs_rs_rs_rs_i1_a;
 +reg _rs_rs_rs_rs_rs_i1_c;
 +reg _rs_rs_rs_rs_rs_i1_b;
 +reg \_rs_rs_rs_rs_rs_i1[6]_b ;
 +reg \_rs_rs_rs_rs_rs_i1[5]_a ;
 +reg \_rs_rs_rs_rs_rs_i1[5]_b ;
 +reg \_rs_rs_rs_rs_rs_i1[4]_b ;
 +reg \_rs_rs_rs_rs_rs_i1[1]_c ;
 +reg _rs_rs_rs_rs_rs_a;
 +reg _rs_rs_rs_rs_rs_c;
 +reg _rs_rs_rs_rs_rs_b;
 +reg \_rs_rs_rs_rs_i1[6]_c ;
 +reg \_rs_rs_rs_rs_i1[6]_b ;
 +reg \_rs_rs_rs_rs_i1[5]_a ;
 +reg \_rs_rs_rs_rs_i1[4]_c ;
 +reg \_rs_rs_rs_rs_i1[3]_b ;
 +reg _rs_rs_rs_rs_a;
 +reg _rs_rs_rs_rs_c;
 +reg _rs_rs_rs_rs_b;
 +reg \_rs_rs_rs_i1[6]_a ;
 +reg \_rs_rs_rs_i1[6]_b ;
 +reg \_rs_rs_rs_i1[5]_c ;
 +reg \_rs_rs_rs_i1[3]_b ;
 +reg \_rs_rs_rs_i1[1]_b ;
 +reg _rs_rs_rs_a;
 +reg _rs_rs_rs_c;
 +reg _rs_rs_rs_b;
 +reg \_rs_rs_i1[6]_c ;
 +reg \_rs_rs_i1[5]_b ;
 +reg \_rs_rs_i1[4]_c ;
 +reg \_rs_rs_i1[3]_c ;
 +reg \_rs_rs_i1[0]_a ;
 +
 +reg _rs_rs_rs_rs_rs_i1_sl1 [0:8-1];
 +reg _rs_rs_rs_rs_rs_i1_sl2 [0:8-1];
 +
 +always @(i7 or i0 or i4) begin: _RandomScrambler_rs_i1_0
 +    \_rs_rs_i1[0]_a  <= (i7 ^ i0 ^ i4);
 +end
 +
 +always @(i6 or i1 or i4) begin: _RandomScrambler_rs_i1_1
 +    \_rs_rs_i1[5]_b  <= (i6 ^ i1 ^ i4);
 +end
 +
 +always @(i5 or i6 or i2) begin: _RandomScrambler_rs_i1_2
 +    \_rs_rs_i1[3]_c  <= (i5 ^ i6 ^ i2);
 +end
 +
 +always @(i4 or i0 or i5) begin: _RandomScrambler_rs_i1_3
 +    \_rs_rs_i1[4]_c  <= (i4 ^ i0 ^ i5);
 +end
 +
 +always @(i3 or i0 or i2) begin: _RandomScrambler_rs_i1_4
 +    _rs_rs_rs_b <= (i3 ^ i0 ^ i2);
 +end
 +
 +always @(i2 or i5 or i7) begin: _RandomScrambler_rs_i1_5
 +    \_rs_rs_i1[6]_c  <= (i2 ^ i5 ^ i7);
 +end
 +
 +always @(i1 or i4 or i7) begin: _RandomScrambler_rs_i1_6
 +    _rs_rs_rs_c <= (i1 ^ i4 ^ i7);
 +end
 +
 +always @(i0 or i5 or i4) begin: _RandomScrambler_rs_i1_7
 +    _rs_rs_rs_a <= (i0 ^ i5 ^ i4);
 +end
 +
 +always @(\_rs_i2[2]_c  or \_rs_i2[7]_a  or \_rs_i2[7]_c ) begin: _RandomScrambler_rs_i2_0
 +    o7 <= (\_rs_i2[2]_c  ^ \_rs_i2[7]_a  ^ \_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_i2[7]_c  or \_rs_i2[4]_a  or \_rs_i2[2]_c ) begin: _RandomScrambler_rs_i2_1
 +    o6 <= (\_rs_i2[7]_c  ^ \_rs_i2[4]_a  ^ \_rs_i2[2]_c );
 +end
 +
 +always @(\_rs_i2[5]_c  or \_rs_i2[7]_a  or \_rs_i2[2]_c ) begin: _RandomScrambler_rs_i2_2
 +    o5 <= (\_rs_i2[5]_c  ^ \_rs_i2[7]_a  ^ \_rs_i2[2]_c );
 +end
 +
 +always @(\_rs_i2[7]_b  or \_rs_i2[7]_c  or \_rs_i2[7]_a ) begin: _RandomScrambler_rs_i2_3
 +    o4 <= (\_rs_i2[7]_b  ^ \_rs_i2[7]_c  ^ \_rs_i2[7]_a );
 +end
 +
 +always @(\_rs_i2[4]_a  or \_rs_i2[6]_a  or \_rs_i2[7]_a ) begin: _RandomScrambler_rs_i2_4
 +    o3 <= (\_rs_i2[4]_a  ^ \_rs_i2[6]_a  ^ \_rs_i2[7]_a );
 +end
 +
 +always @(\_rs_i2[5]_a  or \_rs_i2[7]_b  or \_rs_i2[5]_c ) begin: _RandomScrambler_rs_i2_5
 +    o2 <= (\_rs_i2[5]_a  ^ \_rs_i2[7]_b  ^ \_rs_i2[5]_c );
 +end
 +
 +always @(\_rs_i2[6]_a  or \_rs_i2[7]_b  or \_rs_i2[7]_a ) begin: _RandomScrambler_rs_i2_6
 +    o1 <= (\_rs_i2[6]_a  ^ \_rs_i2[7]_b  ^ \_rs_i2[7]_a );
 +end
 +
 +always @(\_rs_i2[7]_a  or \_rs_i2[7]_b  or \_rs_i2[7]_c ) begin: _RandomScrambler_rs_i2_7
 +    o0 <= (\_rs_i2[7]_a  ^ \_rs_i2[7]_b  ^ \_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_i1[0]_a  or \_rs_rs_i1[6]_c  or \_rs_rs_i1[4]_c ) begin: _RandomScrambler_rs_rs_i1_0
 +    \_rs_rs_rs_i1[1]_b  <= (\_rs_rs_i1[0]_a  ^ \_rs_rs_i1[6]_c  ^ \_rs_rs_i1[4]_c );
 +end
 +
 +always @(\_rs_rs_i1[5]_b  or \_rs_rs_i1[6]_c  or \_rs_rs_i1[4]_c ) begin: _RandomScrambler_rs_rs_i1_1
 +    \_rs_rs_rs_i1[3]_b  <= (\_rs_rs_i1[5]_b  ^ \_rs_rs_i1[6]_c  ^ \_rs_rs_i1[4]_c );
 +end
 +
 +always @(\_rs_rs_i1[3]_c  or _rs_rs_rs_a or _rs_rs_rs_c) begin: _RandomScrambler_rs_rs_i1_2
 +    \_rs_rs_rs_i1[5]_c  <= (\_rs_rs_i1[3]_c  ^ _rs_rs_rs_a ^ _rs_rs_rs_c);
 +end
 +
 +always @(\_rs_rs_i1[4]_c  or _rs_rs_rs_a or \_rs_rs_i1[3]_c ) begin: _RandomScrambler_rs_rs_i1_3
 +    _rs_rs_rs_rs_b <= (\_rs_rs_i1[4]_c  ^ _rs_rs_rs_a ^ \_rs_rs_i1[3]_c );
 +end
 +
 +always @(_rs_rs_rs_b or \_rs_rs_i1[6]_c  or \_rs_rs_i1[4]_c ) begin: _RandomScrambler_rs_rs_i1_4
 +    \_rs_rs_rs_i1[6]_b  <= (_rs_rs_rs_b ^ \_rs_rs_i1[6]_c  ^ \_rs_rs_i1[4]_c );
 +end
 +
 +always @(\_rs_rs_i1[6]_c  or \_rs_rs_i1[5]_b  or _rs_rs_rs_b) begin: _RandomScrambler_rs_rs_i1_5
 +    _rs_rs_rs_rs_c <= (\_rs_rs_i1[6]_c  ^ \_rs_rs_i1[5]_b  ^ _rs_rs_rs_b);
 +end
 +
 +always @(_rs_rs_rs_c or _rs_rs_rs_b or \_rs_rs_i1[6]_c ) begin: _RandomScrambler_rs_rs_i1_6
 +    \_rs_rs_rs_i1[6]_a  <= (_rs_rs_rs_c ^ _rs_rs_rs_b ^ \_rs_rs_i1[6]_c );
 +
 +end
 +
 +
 +always @(_rs_rs_rs_a or _rs_rs_rs_b or _rs_rs_rs_c) begin: _RandomScrambler_rs_rs_i1_7
 +    _rs_rs_rs_rs_a <= (_rs_rs_rs_a ^ _rs_rs_rs_b ^ _rs_rs_rs_c);
 +end
 +
 +always @(\_rs_rs_i2[7]_c  or \_rs_rs_i2[6]_a  or \_rs_rs_i2[7]_b ) begin: _RandomScrambler_rs_rs_i2_0
 +    \_rs_i2[2]_c  <= (\_rs_rs_i2[7]_c  ^ \_rs_rs_i2[6]_a  ^ \_rs_rs_i2[7]_b );
 +end
 +
 +always @(\_rs_rs_i2[6]_c  or \_rs_rs_i2[5]_c  or \_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_i2_1
 +    \_rs_i2[7]_c  <= (\_rs_rs_i2[6]_c  ^ \_rs_rs_i2[5]_c  ^ \_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_i2[7]_b  or \_rs_rs_i2[6]_b  or \_rs_rs_i2[7]_a ) begin: _RandomScrambler_rs_rs_i2_2
 +    \_rs_i2[5]_c  <= (\_rs_rs_i2[7]_b  ^ \_rs_rs_i2[6]_b  ^ \_rs_rs_i2[7]_a );
 +end
 +
 +always @(\_rs_rs_i2[6]_b  or \_rs_rs_i2[6]_c  or \_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_i2_3
 +    \_rs_i2[7]_b  <= (\_rs_rs_i2[6]_b  ^ \_rs_rs_i2[6]_c  ^ \_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_i2[5]_c  or \_rs_rs_i2[7]_a  or \_rs_rs_i2[7]_b ) begin: _RandomScrambler_rs_rs_i2_4
 +    \_rs_i2[4]_a  <= (\_rs_rs_i2[5]_c  ^ \_rs_rs_i2[7]_a  ^ \_rs_rs_i2[7]_b );
 +end
 +
 +always @(\_rs_rs_i2[5]_a  or \_rs_rs_i2[6]_a  or \_rs_rs_i2[5]_c ) begin: _RandomScrambler_rs_rs_i2_5
 +    \_rs_i2[5]_a  <= (\_rs_rs_i2[5]_a  ^ \_rs_rs_i2[6]_a  ^ \_rs_rs_i2[5]_c );
 +end
 +
 +always @(\_rs_rs_i2[6]_a  or \_rs_rs_i2[6]_b  or \_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_i2_6
 +    \_rs_i2[6]_a  <= (\_rs_rs_i2[6]_a  ^ \_rs_rs_i2[6]_b  ^ \_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_i2[7]_a  or \_rs_rs_i2[7]_b  or \_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_i2_7
 +    \_rs_i2[7]_a  <= (\_rs_rs_i2[7]_a  ^ \_rs_rs_i2[7]_b  ^ \_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_rs_i1[1]_b  or _rs_rs_rs_rs_c or _rs_rs_rs_rs_a) begin: _RandomScrambler_rs_rs_rs_i1_0
 +    \_rs_rs_rs_rs_i1[6]_b  <= (\_rs_rs_rs_i1[1]_b  ^ _rs_rs_rs_rs_c ^ _rs_rs_rs_rs_a);
 +end
 +
 +always @(\_rs_rs_rs_i1[3]_b  or \_rs_rs_rs_i1[1]_b  or \_rs_rs_rs_i1[6]_a ) begin: _RandomScrambler_rs_rs_rs_i1_1
 +    \_rs_rs_rs_rs_i1[4]_c  <= (\_rs_rs_rs_i1[3]_b  ^ \_rs_rs_rs_i1[1]_b  ^ \_rs_rs_rs_i1[6]_a );
 +end
 +
 +always @(\_rs_rs_rs_i1[5]_c  or \_rs_rs_rs_i1[6]_b  or \_rs_rs_rs_i1[3]_b ) begin: _RandomScrambler_rs_rs_rs_i1_2
 +    \_rs_rs_rs_rs_i1[3]_b  <= (\_rs_rs_rs_i1[5]_c  ^ \_rs_rs_rs_i1[6]_b  ^ \_rs_rs_rs_i1[3]_b );
 +end
 +
 +always @(_rs_rs_rs_rs_b or \_rs_rs_rs_i1[3]_b  or \_rs_rs_rs_i1[6]_a ) begin: _RandomScrambler_rs_rs_rs_i1_3
 +    _rs_rs_rs_rs_rs_c <= (_rs_rs_rs_rs_b ^ \_rs_rs_rs_i1[3]_b  ^ \_rs_rs_rs_i1[6]_a );
 +end
 +
 +always @(\_rs_rs_rs_i1[6]_b  or _rs_rs_rs_rs_b or _rs_rs_rs_rs_a) begin: _RandomScrambler_rs_rs_rs_i1_4
 +    \_rs_rs_rs_rs_i1[6]_c  <= (\_rs_rs_rs_i1[6]_b  ^ _rs_rs_rs_rs_b ^ _rs_rs_rs_rs_a);
 +end
 +
 +always @(_rs_rs_rs_rs_c or \_rs_rs_rs_i1[6]_a  or \_rs_rs_rs_i1[5]_c ) begin: _RandomScrambler_rs_rs_rs_i1_5
 +
 +    \_rs_rs_rs_rs_i1[5]_a  <= (_rs_rs_rs_rs_c ^ \_rs_rs_rs_i1[6]_a  ^ \_rs_rs_rs_i1[5]_c );
 +end
 +
 +always @(\_rs_rs_rs_i1[6]_a  or \_rs_rs_rs_i1[6]_b  or _rs_rs_rs_rs_b) begin: _RandomScrambler_rs_rs_rs_i1_6
 +    _rs_rs_rs_rs_rs_b <= (\_rs_rs_rs_i1[6]_a  ^ \_rs_rs_rs_i1[6]_b  ^ _rs_rs_rs_rs_b);
 +end
 +
 +always @(_rs_rs_rs_rs_a or _rs_rs_rs_rs_b or _rs_rs_rs_rs_c) begin: _RandomScrambler_rs_rs_rs_i1_7
 +    _rs_rs_rs_rs_rs_a <= (_rs_rs_rs_rs_a ^ _rs_rs_rs_rs_b ^ _rs_rs_rs_rs_c);
 +end
 +
 +always @(\_rs_rs_rs_i2[5]_c  or \_rs_rs_rs_i2[6]_b  or \_rs_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_rs_i2_0
 +    \_rs_rs_i2[7]_c  <= (\_rs_rs_rs_i2[5]_c  ^ \_rs_rs_rs_i2[6]_b  ^ \_rs_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_i2[3]_a  or \_rs_rs_rs_i2[6]_b ) begin: _RandomScrambler_rs_rs_rs_i2_1
 +    \_rs_rs_i2[6]_c  <= (\_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_i2[3]_a  ^ \_rs_rs_rs_i2[6]_b );
 +end
 +
 +always @(\_rs_rs_rs_i2[6]_b  or \_rs_rs_rs_i2[3]_a  or \_rs_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_rs_i2_2
 +    \_rs_rs_i2[7]_b  <= (\_rs_rs_rs_i2[6]_b  ^ \_rs_rs_rs_i2[3]_a  ^ \_rs_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_i2[3]_a  or \_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_i2[6]_b ) begin: _RandomScrambler_rs_rs_rs_i2_3
 +    \_rs_rs_i2[6]_b  <= (\_rs_rs_rs_i2[3]_a  ^ \_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_i2[6]_b );
 +end
 +
 +always @(\_rs_rs_rs_i2[6]_c  or \_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_i2[5]_a ) begin: _RandomScrambler_rs_rs_rs_i2_4
 +    \_rs_rs_i2[5]_c  <= (\_rs_rs_rs_i2[6]_c  ^ \_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_i2[5]_a );
 +end
 +
 +always @(\_rs_rs_rs_i2[5]_a  or \_rs_rs_rs_i2[6]_b  or \_rs_rs_rs_i2[5]_c ) begin: _RandomScrambler_rs_rs_rs_i2_5
 +    \_rs_rs_i2[5]_a  <= (\_rs_rs_rs_i2[5]_a  ^ \_rs_rs_rs_i2[6]_b  ^ \_rs_rs_rs_i2[5]_c );
 +end
 +
 +always @(\_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_i2[6]_b  or \_rs_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_rs_i2_6
 +    \_rs_rs_i2[6]_a  <= (\_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_i2[6]_b  ^ \_rs_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_i2[7]_a  or \_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_rs_i2_7
 +    \_rs_rs_i2[7]_a  <= (\_rs_rs_rs_i2[7]_a  ^ \_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_i1[6]_b  or \_rs_rs_rs_rs_i1[6]_c  or \_rs_rs_rs_rs_i1[5]_a ) begin: _RandomScrambler_rs_rs_rs_rs_i1_0
 +    \_rs_rs_rs_rs_rs_i1[1]_c  <= (\_rs_rs_rs_rs_i1[6]_b  ^ \_rs_rs_rs_rs_i1[6]_c  ^ \_rs_rs_rs_rs_i1[5]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_i1[4]_c  or _rs_rs_rs_rs_rs_c or \_rs_rs_rs_rs_i1[6]_b ) begin: _RandomScrambler_rs_rs_rs_rs_i1_1
 +    \_rs_rs_rs_rs_rs_i1[6]_b  <= (\_rs_rs_rs_rs_i1[4]_c  ^ _rs_rs_rs_rs_rs_c ^ \_rs_rs_rs_rs_i1[6]_b );
 +end
 +
 +always @(\_rs_rs_rs_rs_i1[3]_b  or \_rs_rs_rs_rs_i1[5]_a  or _rs_rs_rs_rs_rs_c) begin: _RandomScrambler_rs_rs_rs_rs_i1_2
 +    \_rs_rs_rs_rs_rs_i1[5]_b  <= (\_rs_rs_rs_rs_i1[3]_b  ^ \_rs_rs_rs_rs_i1[5]_a  ^ _rs_rs_rs_rs_rs_c);
 +end
 +
 +always @(_rs_rs_rs_rs_rs_c or \_rs_rs_rs_rs_i1[3]_b  or \_rs_rs_rs_rs_i1[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i1_3
 +    \_rs_rs_rs_rs_rs_i1[4]_b  <= (_rs_rs_rs_rs_rs_c ^ \_rs_rs_rs_rs_i1[3]_b  ^ \_rs_rs_rs_rs_i1[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_i1[6]_c  or _rs_rs_rs_rs_rs_a or \_rs_rs_rs_rs_i1[4]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i1_4
 +    _rs_rs_rs_rs_rs_i1_b <= (\_rs_rs_rs_rs_i1[6]_c  ^ _rs_rs_rs_rs_rs_a ^ \_rs_rs_rs_rs_i1[4]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_i1[5]_a  or \_rs_rs_rs_rs_i1[6]_c  or _rs_rs_rs_rs_rs_c) begin: _RandomScrambler_rs_rs_rs_rs_i1_5
 +    \_rs_rs_rs_rs_rs_i1[5]_a  <= (\_rs_rs_rs_rs_i1[5]_a  ^ \_rs_rs_rs_rs_i1[6]_c  ^ _rs_rs_rs_rs_rs_c);
 +end
 +
 +always @(_rs_rs_rs_rs_rs_b or \_rs_rs_rs_rs_i1[6]_b  or \_rs_rs_rs_rs_i1[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i1_6
 +    _rs_rs_rs_rs_rs_i1_c <= (_rs_rs_rs_rs_rs_b ^ \_rs_rs_rs_rs_i1[6]_b  ^ \_rs_rs_rs_rs_i1[6]_c );
 +end
 +
 +always @(_rs_rs_rs_rs_rs_a or _rs_rs_rs_rs_rs_b or _rs_rs_rs_rs_rs_c) begin: _RandomScrambler_rs_rs_rs_rs_i1_7
 +    _rs_rs_rs_rs_rs_i1_a <= (_rs_rs_rs_rs_rs_a ^ _rs_rs_rs_rs_rs_b ^ _rs_rs_rs_rs_rs_c);
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[4]_c  or \_rs_rs_rs_rs_i2[6]_c  or \_rs_rs_rs_rs_i2[7]_a ) begin: _RandomScrambler_rs_rs_rs_rs_i2_0
 +    \_rs_rs_rs_i2[5]_c  <= (\_rs_rs_rs_rs_i2[4]_c  ^ \_rs_rs_rs_rs_i2[6]_c  ^ \_rs_rs_rs_rs_i2[7]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[6]_c  or \_rs_rs_rs_rs_i2[5]_a  or \_rs_rs_rs_rs_i2[7]_a ) begin: _RandomScrambler_rs_rs_rs_rs_i2_1
 +    \_rs_rs_rs_i2[7]_c  <= (\_rs_rs_rs_rs_i2[6]_c  ^ \_rs_rs_rs_rs_i2[5]_a  ^ \_rs_rs_rs_rs_i2[7]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[4]_b  or \_rs_rs_rs_rs_i2[4]_c  or \_rs_rs_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i2_2
 +    \_rs_rs_rs_i2[6]_b  <= (\_rs_rs_rs_rs_i2[4]_b  ^ \_rs_rs_rs_rs_i2[4]_c  ^ \_rs_rs_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_rs_i2[5]_a ) begin: _RandomScrambler_rs_rs_rs_rs_i2_3
 +    \_rs_rs_rs_i2[3]_a  <= (\_rs_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_rs_i2[5]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_rs_i2[4]_b  or \_rs_rs_rs_rs_i2[4]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i2_4
 +    \_rs_rs_rs_i2[6]_c  <= (\_rs_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_rs_i2[4]_b  ^ \_rs_rs_rs_rs_i2[4]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[5]_a  or \_rs_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_rs_i2[6]_a ) begin: _RandomScrambler_rs_rs_rs_rs_i2_5
 +    \_rs_rs_rs_i2[5]_a  <= (\_rs_rs_rs_rs_i2[5]_a  ^ \_rs_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_rs_i2[6]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[6]_a  or \_rs_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i2_6
 +    \_rs_rs_rs_i2[7]_b  <= (\_rs_rs_rs_rs_i2[6]_a  ^ \_rs_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_i2[7]_a  or \_rs_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_rs_rs_i2_7
 +    \_rs_rs_rs_i2[7]_a  <= (\_rs_rs_rs_rs_i2[7]_a  ^ \_rs_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1[1]_c  or _rs_rs_rs_rs_rs_i1_a or \_rs_rs_rs_rs_rs_i1[5]_a ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_0
 +    \_rs_rs_rs_rs_rs_i1_i1[6]_c  <= (\_rs_rs_rs_rs_rs_i1[1]_c  ^ _rs_rs_rs_rs_rs_i1_a ^ \_rs_rs_rs_rs_rs_i1[5]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1[6]_b  or \_rs_rs_rs_rs_rs_i1[5]_a  or \_rs_rs_rs_rs_rs_i1[1]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_1
 +    \_rs_rs_rs_rs_rs_i1_i1[1]_a  <= (\_rs_rs_rs_rs_rs_i1[6]_b  ^ \_rs_rs_rs_rs_rs_i1[5]_a  ^ \_rs_rs_rs_rs_rs_i1[1]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1[5]_b  or _rs_rs_rs_rs_rs_i1_a or _rs_rs_rs_rs_rs_i1_c) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_2
 +    \_rs_rs_rs_rs_rs_i1_i1[5]_b  <= (\_rs_rs_rs_rs_rs_i1[5]_b  ^ _rs_rs_rs_rs_rs_i1_a ^ _rs_rs_rs_rs_rs_i1_c);
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1[4]_b  or \_rs_rs_rs_rs_rs_i1[5]_a  or _rs_rs_rs_rs_rs_i1_a) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_3
 +    \_rs_rs_rs_rs_rs_i1_i1[4]_c  <= (\_rs_rs_rs_rs_rs_i1[4]_b  ^ \_rs_rs_rs_rs_rs_i1[5]_a  ^ _rs_rs_rs_rs_rs_i1_a);
 +end
 +
 +always @(_rs_rs_rs_rs_rs_i1_b or \_rs_rs_rs_rs_rs_i1[4]_b  or \_rs_rs_rs_rs_rs_i1[6]_b ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_4
 +    \_rs_rs_rs_rs_rs_i1_i1[7]_b  <= (_rs_rs_rs_rs_rs_i1_b ^ \_rs_rs_rs_rs_rs_i1[4]_b  ^ \_rs_rs_rs_rs_rs_i1[6]_b );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1[5]_a  or \_rs_rs_rs_rs_rs_i1[5]_b  or _rs_rs_rs_rs_rs_i1_a) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_5
 +    \_rs_rs_rs_rs_rs_i1_i1[7]_c  <= (\_rs_rs_rs_rs_rs_i1[5]_a  ^ \_rs_rs_rs_rs_rs_i1[5]_b  ^ _rs_rs_rs_rs_rs_i1_a);
 +end
 +
 +always @(_rs_rs_rs_rs_rs_i1_c or \_rs_rs_rs_rs_rs_i1[6]_b  or _rs_rs_rs_rs_rs_i1_b) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_6
 +    \_rs_rs_rs_rs_rs_i1_i1[6]_a  <= (_rs_rs_rs_rs_rs_i1_c ^ \_rs_rs_rs_rs_rs_i1[6]_b  ^ _rs_rs_rs_rs_rs_i1_b);
 +end
 +
 +always @(_rs_rs_rs_rs_rs_i1_a or _rs_rs_rs_rs_rs_i1_b or _rs_rs_rs_rs_rs_i1_c) begin: _RandomScrambler_rs_rs_rs_rs_rs_i1_7
 +    \_rs_rs_rs_rs_rs_i1_i1[7]_a  <= (_rs_rs_rs_rs_rs_i1_a ^ _rs_rs_rs_rs_rs_i1_b ^ _rs_rs_rs_rs_rs_i1_c);
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_rs_rs_i2[5]_a  or \_rs_rs_rs_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_0
 +    \_rs_rs_rs_rs_i2[4]_c  <= (\_rs_rs_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_rs_rs_i2[5]_a  ^ \_rs_rs_rs_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[1]_a  or \_rs_rs_rs_rs_rs_i2[4]_c  or \_rs_rs_rs_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_1
 +    \_rs_rs_rs_rs_i2[6]_c  <= (\_rs_rs_rs_rs_rs_i2[1]_a  ^ \_rs_rs_rs_rs_rs_i2[4]_c  ^ \_rs_rs_rs_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[4]_c  or \_rs_rs_rs_rs_rs_i2[6]_c  or \_rs_rs_rs_rs_rs_i2[6]_a ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_2
 +    \_rs_rs_rs_rs_i2[4]_b  <= (\_rs_rs_rs_rs_rs_i2[4]_c  ^ \_rs_rs_rs_rs_rs_i2[6]_c  ^ \_rs_rs_rs_rs_rs_i2[6]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_rs_rs_i2[7]_a  or \_rs_rs_rs_rs_rs_i2[5]_a ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_3
 +    \_rs_rs_rs_rs_i2[7]_c  <= (\_rs_rs_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_rs_rs_i2[7]_a  ^ \_rs_rs_rs_rs_rs_i2[5]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[6]_c  or \_rs_rs_rs_rs_rs_i2[6]_a  or \_rs_rs_rs_rs_rs_i2[4]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_4
 +    \_rs_rs_rs_rs_i2[7]_b  <= (\_rs_rs_rs_rs_rs_i2[6]_c  ^ \_rs_rs_rs_rs_rs_i2[6]_a  ^ \_rs_rs_rs_rs_rs_i2[4]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[5]_a  or \_rs_rs_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_rs_rs_i2[7]_b ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_5
 +    \_rs_rs_rs_rs_i2[5]_a  <= (\_rs_rs_rs_rs_rs_i2[5]_a  ^ \_rs_rs_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_rs_rs_i2[7]_b );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[6]_a  or \_rs_rs_rs_rs_rs_i2[7]_c  or \_rs_rs_rs_rs_rs_i2[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_6
 +    \_rs_rs_rs_rs_i2[6]_a  <= (\_rs_rs_rs_rs_rs_i2[6]_a  ^ \_rs_rs_rs_rs_rs_i2[7]_c  ^ \_rs_rs_rs_rs_rs_i2[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i2[7]_a  or \_rs_rs_rs_rs_rs_i2[7]_b  or \_rs_rs_rs_rs_rs_i2[7]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_i2_7
 +    \_rs_rs_rs_rs_i2[7]_a  <= (\_rs_rs_rs_rs_rs_i2[7]_a  ^ \_rs_rs_rs_rs_rs_i2[7]_b  ^ \_rs_rs_rs_rs_rs_i2[7]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[6]_c  or \_rs_rs_rs_rs_rs_i1_i1[7]_b  or \_rs_rs_rs_rs_rs_i1_i1[5]_b ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_0
 +    \_rs_rs_rs_rs_rs_i2[7]_b  <= (\_rs_rs_rs_rs_rs_i1_i1[6]_c  ^ \_rs_rs_rs_rs_rs_i1_i1[7]_b  ^ \_rs_rs_rs_rs_rs_i1_i1[5]_b );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[1]_a  or \_rs_rs_rs_rs_rs_i1_i1[4]_c  or \_rs_rs_rs_rs_rs_i1_i1[6]_a ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_1
 +    \_rs_rs_rs_rs_rs_i2[1]_a  <= (\_rs_rs_rs_rs_rs_i1_i1[1]_a  ^ \_rs_rs_rs_rs_rs_i1_i1[4]_c  ^ \_rs_rs_rs_rs_rs_i1_i1[6]_a );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[5]_b  or \_rs_rs_rs_rs_rs_i1_i1[6]_c  or \_rs_rs_rs_rs_rs_i1_i1[4]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_2
 +    \_rs_rs_rs_rs_rs_i2[4]_c  <= (\_rs_rs_rs_rs_rs_i1_i1[5]_b  ^ \_rs_rs_rs_rs_rs_i1_i1[6]_c  ^ \_rs_rs_rs_rs_rs_i1_i1[4]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[4]_c  or \_rs_rs_rs_rs_rs_i1_i1[6]_a  or \_rs_rs_rs_rs_rs_i1_i1[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_3
 +    \_rs_rs_rs_rs_rs_i2[7]_c  <= (\_rs_rs_rs_rs_rs_i1_i1[4]_c  ^ \_rs_rs_rs_rs_rs_i1_i1[6]_a  ^ \_rs_rs_rs_rs_rs_i1_i1[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[7]_b  or \_rs_rs_rs_rs_rs_i1_i1[7]_a  or \_rs_rs_rs_rs_rs_i1_i1[4]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_4
 +    \_rs_rs_rs_rs_rs_i2[6]_c  <= (\_rs_rs_rs_rs_rs_i1_i1[7]_b  ^ \_rs_rs_rs_rs_rs_i1_i1[7]_a  ^ \_rs_rs_rs_rs_rs_i1_i1[4]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[7]_c  or \_rs_rs_rs_rs_rs_i1_i1[5]_b  or \_rs_rs_rs_rs_rs_i1_i1[7]_b ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_5
 +    \_rs_rs_rs_rs_rs_i2[5]_a  <= (\_rs_rs_rs_rs_rs_i1_i1[7]_c  ^ \_rs_rs_rs_rs_rs_i1_i1[5]_b  ^ \_rs_rs_rs_rs_rs_i1_i1[7]_b );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[6]_a  or \_rs_rs_rs_rs_rs_i1_i1[7]_c  or \_rs_rs_rs_rs_rs_i1_i1[6]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_6
 +    \_rs_rs_rs_rs_rs_i2[6]_a  <= (\_rs_rs_rs_rs_rs_i1_i1[6]_a  ^ \_rs_rs_rs_rs_rs_i1_i1[7]_c  ^ \_rs_rs_rs_rs_rs_i1_i1[6]_c );
 +end
 +
 +always @(\_rs_rs_rs_rs_rs_i1_i1[7]_a  or \_rs_rs_rs_rs_rs_i1_i1[7]_b  or \_rs_rs_rs_rs_rs_i1_i1[7]_c ) begin: _RandomScrambler_rs_rs_rs_rs_rs_rs_i1_7
 +    \_rs_rs_rs_rs_rs_i2[7]_a  <= (\_rs_rs_rs_rs_rs_i1_i1[7]_a  ^ \_rs_rs_rs_rs_rs_i1_i1[7]_b  ^ \_rs_rs_rs_rs_rs_i1_i1[7]_c );
 +end
 +
 +endmodule
 +module rom1 (
 +    dout,
 +    addr,
 +    clk
 +);
 +
 +output [7:0] dout;
 +reg [7:0] dout;
 +input [7:0] addr;
 +input clk;
 +
 +
 +
 +always @(posedge clk) begin: _rom1_RL
 +    // synthesis parallel_case full_case
 +    case (addr)
 +        0: dout <= 244;
 +        1: dout <= 242;
 +        2: dout <= 14;
 +        3: dout <= 21;
 +        4: dout <= 213;
 +        5: dout <= 188;
 +        6: dout <= 171;
 +        7: dout <= 78;
 +        8: dout <= 155;
 +        9: dout <= 155;
 +        10: dout <= 148;
 +        11: dout <= 40;
 +        12: dout <= 110;
 +        13: dout <= 100;
 +        14: dout <= 185;
 +        15: dout <= 254;
 +        16: dout <= 243;
 +        17: dout <= 139;
 +        18: dout <= 113;
 +        19: dout <= 68;
 +        20: dout <= 9;
 +        21: dout <= 7;
 +        22: dout <= 119;
 +        23: dout <= 81;
 +        24: dout <= 97;
 +        25: dout <= 228;
 +        26: dout <= 134;
 +        27: dout <= 143;
 +        28: dout <= 60;
 +        29: dout <= 6;
 +        30: dout <= 83;
 +        31: dout <= 34;
 +        32: dout <= 130;
 +        33: dout <= 255;
 +        34: dout <= 172;
 +        35: dout <= 46;
 +        36: dout <= 228;
 +        37: dout <= 203;
 +        38: dout <= 188;
 +        39: dout <= 232;
 +        40: dout <= 195;
 +        41: dout <= 202;
 +        42: dout <= 90;
 +        43: dout <= 251;
 +        44: dout <= 246;
 +        45: dout <= 41;
 +        46: dout <= 193;
 +        47: dout <= 183;
 +        48: dout <= 118;
 +        49: dout <= 135;
 +        50: dout <= 125;
 +        51: dout <= 236;
 +        52: dout <= 128;
 +        53: dout <= 212;
 +        54: dout <= 90;
 +        55: dout <= 226;
 +        56: dout <= 230;
 +        57: dout <= 118;
 +        58: dout <= 145;
 +        59: dout <= 235;
 +        60: dout <= 185;
 +        61: dout <= 124;
 +        62: dout <= 56;
 +        63: dout <= 83;
 +        64: dout <= 179;
 +        65: dout <= 42;
 +        66: dout <= 232;
 +        67: dout <= 68;
 +        68: dout <= 233;
 +        69: dout <= 79;
 +        70: dout <= 245;
 +        71: dout <= 180;
 +        72: dout <= 129;
 +        73: dout <= 132;
 +        74: dout <= 166;
 +        75: dout <= 150;
 +        76: dout <= 79;
 +        77: dout <= 53;
 +        78: dout <= 131;
 +        79: dout <= 239;
 +        80: dout <= 159;
 +        81: dout <= 19;
 +        82: dout <= 210;
 +        83: dout <= 185;
 +        84: dout <= 232;
 +        85: dout <= 48;
 +        86: dout <= 190;
 +        87: dout <= 15;
 +        88: dout <= 167;
 +        89: dout <= 69;
 +        90: dout <= 58;
 +        91: dout <= 224;
 +        92: dout <= 27;
 +        93: dout <= 133;
 +        94: dout <= 218;
 +        95: dout <= 62;
 +        96: dout <= 53;
 +        97: dout <= 225;
 +        98: dout <= 108;
 +        99: dout <= 183;
 +        100: dout <= 8;
 +        101: dout <= 92;
 +        102: dout <= 44;
 +        103: dout <= 172;
 +        104: dout <= 21;
 +        105: dout <= 244;
 +        106: dout <= 6;
 +        107: dout <= 186;
 +        108: dout <= 5;
 +        109: dout <= 65;
 +        110: dout <= 208;
 +        111: dout <= 40;
 +        112: dout <= 47;
 +        113: dout <= 177;
 +        114: dout <= 98;
 +        115: dout <= 11;
 +        116: dout <= 253;
 +        117: dout <= 38;
 +        118: dout <= 9;
 +        119: dout <= 88;
 +        120: dout <= 157;
 +        121: dout <= 190;
 +        122: dout <= 28;
 +        123: dout <= 86;
 +        124: dout <= 7;
 +        125: dout <= 114;
 +        126: dout <= 196;
 +        127: dout <= 189;
 +        128: dout <= 230;
 +        129: dout <= 193;
 +        130: dout <= 220;
 +        131: dout <= 180;
 +        132: dout <= 121;
 +        133: dout <= 57;
 +        134: dout <= 169;
 +        135: dout <= 80;
 +        136: dout <= 26;
 +        137: dout <= 114;
 +        138: dout <= 223;
 +        139: dout <= 32;
 +        140: dout <= 149;
 +        141: dout <= 100;
 +        142: dout <= 131;
 +        143: dout <= 36;
 +        144: dout <= 245;
 +        145: dout <= 66;
 +        146: dout <= 155;
 +        147: dout <= 107;
 +        148: dout <= 4;
 +        149: dout <= 142;
 +        150: dout <= 35;
 +        151: dout <= 14;
 +        152: dout <= 8;
 +        153: dout <= 41;
 +        154: dout <= 24;
 +        155: dout <= 162;
 +
 +        156: dout <= 130;
 +        157: dout <= 251;
 +        158: dout <= 239;
 +        159: dout <= 254;
 +        160: dout <= 59;
 +        161: dout <= 113;
 +        162: dout <= 64;
 +        163: dout <= 151;
 +        164: dout <= 159;
 +        165: dout <= 204;
 +        166: dout <= 181;
 +        167: dout <= 65;
 +        168: dout <= 108;
 +        169: dout <= 134;
 +        170: dout <= 1;
 +        171: dout <= 9;
 +        172: dout <= 104;
 +        173: dout <= 28;
 +        174: dout <= 185;
 +        175: dout <= 61;
 +        176: dout <= 25;
 +        177: dout <= 46;
 +        178: dout <= 59;
 +        179: dout <= 55;
 +        180: dout <= 133;
 +        181: dout <= 118;
 +        182: dout <= 79;
 +        183: dout <= 164;
 +        184: dout <= 54;
 +        185: dout <= 232;
 +        186: dout <= 246;
 +        187: dout <= 186;
 +        188: dout <= 111;
 +        189: dout <= 130;
 +        190: dout <= 148;
 +        191: dout <= 13;
 +        192: dout <= 107;
 +        193: dout <= 134;
 +        194: dout <= 46;
 +        195: dout <= 24;
 +        196: dout <= 205;
 +        197: dout <= 93;
 +        198: dout <= 132;
 +        199: dout <= 235;
 +        200: dout <= 156;
 +        201: dout <= 74;
 +        202: dout <= 251;
 +        203: dout <= 95;
 +
 +        204: dout <= 4;
 +        205: dout <= 175;
 +        206: dout <= 25;
 +        207: dout <= 78;
 +        208: dout <= 215;
 +        209: dout <= 172;
 +        210: dout <= 4;
 +        211: dout <= 115;
 +        212: dout <= 105;
 +        213: dout <= 124;
 +        214: dout <= 53;
 +        215: dout <= 150;
 +        216: dout <= 18;
 +        217: dout <= 72;
 +        218: dout <= 95;
 +        219: dout <= 239;
 +        220: dout <= 19;
 +        221: dout <= 193;
 +        222: dout <= 49;
 +        223: dout <= 146;
 +        224: dout <= 100;
 +        225: dout <= 118;
 +        226: dout <= 192;
 +        227: dout <= 101;
 +        228: dout <= 31;
 +        229: dout <= 31;
 +        230: dout <= 20;
 +        231: dout <= 217;
 +        232: dout <= 164;
 +        233: dout <= 245;
 +        234: dout <= 177;
 +        235: dout <= 6;
 +        236: dout <= 168;
 +        237: dout <= 198;
 +        238: dout <= 185;
 +        239: dout <= 127;
 +        240: dout <= 91;
 +        241: dout <= 117;
 +        242: dout <= 204;
 +        243: dout <= 68;
 +        244: dout <= 134;
 +        245: dout <= 122;
 +        246: dout <= 244;
 +        247: dout <= 205;
 +        248: dout <= 238;
 +        249: dout <= 214;
 +        250: dout <= 75;
 +        251: dout <= 59;
 +        252: dout <= 125;
 +        253: dout <= 66;
 +        254: dout <= 109;
 +        default: dout <= 173;
 +    endcase
 +end
 +
 +endmodule
 +module rom2 (
 +    dout,
 +    addr,
 +    clk
 +);
 +
 +output [7:0] dout;
 +reg [7:0] dout;
 +input [7:0] addr;
 +input clk;
 +
 +
 +
 +always @(posedge clk) begin: _rom2_RL
 +    // synthesis parallel_case full_case
 +    case (addr)
 +        0: dout <= 244;
 +        1: dout <= 242;
 +        2: dout <= 14;
 +        3: dout <= 21;
 +        4: dout <= 213;
 +        5: dout <= 188;
 +        6: dout <= 171;
 +        7: dout <= 78;
 +        8: dout <= 155;
 +        9: dout <= 155;
 +        10: dout <= 148;
 +        11: dout <= 40;
 +        12: dout <= 110;
 +        13: dout <= 100;
 +        14: dout <= 185;
 +        15: dout <= 254;
 +        16: dout <= 243;
 +        17: dout <= 139;
 +        18: dout <= 113;
 +        19: dout <= 68;
 +        20: dout <= 9;
 +        21: dout <= 7;
 +        22: dout <= 119;
 +        23: dout <= 81;
 +        24: dout <= 97;
 +        25: dout <= 228;
 +        26: dout <= 134;
 +        27: dout <= 143;
 +        28: dout <= 60;
 +        29: dout <= 6;
 +        30: dout <= 83;
 +        31: dout <= 34;
 +        32: dout <= 130;
 +        33: dout <= 255;
 +        34: dout <= 172;
 +        35: dout <= 46;
 +        36: dout <= 228;
 +        37: dout <= 203;
 +        38: dout <= 188;
 +        39: dout <= 232;
 +        40: dout <= 195;
 +        41: dout <= 202;
 +        42: dout <= 90;
 +        43: dout <= 251;
 +        44: dout <= 246;
 +        45: dout <= 41;
 +        46: dout <= 193;
 +        47: dout <= 183;
 +        48: dout <= 118;
 +        49: dout <= 135;
 +        50: dout <= 125;
 +        51: dout <= 236;
 +        52: dout <= 128;
 +        53: dout <= 212;
 +        54: dout <= 90;
 +        55: dout <= 226;
 +        56: dout <= 230;
 +        57: dout <= 118;
 +        58: dout <= 145;
 +        59: dout <= 235;
 +        60: dout <= 185;
 +        61: dout <= 124;
 +        62: dout <= 56;
 +        63: dout <= 83;
 +        64: dout <= 179;
 +        65: dout <= 42;
 +        66: dout <= 232;
 +        67: dout <= 68;
 +        68: dout <= 233;
 +        69: dout <= 79;
 +        70: dout <= 245;
 +        71: dout <= 180;
 +        72: dout <= 129;
 +        73: dout <= 132;
 +        74: dout <= 166;
 +        75: dout <= 150;
 +        76: dout <= 79;
 +        77: dout <= 53;
 +        78: dout <= 131;
 +        79: dout <= 239;
 +        80: dout <= 159;
 +        81: dout <= 19;
 +        82: dout <= 210;
 +        83: dout <= 185;
 +        84: dout <= 232;
 +        85: dout <= 48;
 +        86: dout <= 190;
 +        87: dout <= 15;
 +        88: dout <= 167;
 +        89: dout <= 69;
 +        90: dout <= 58;
 +        91: dout <= 224;
 +        92: dout <= 27;
 +        93: dout <= 133;
 +        94: dout <= 218;
 +        95: dout <= 62;
 +        96: dout <= 53;
 +        97: dout <= 225;
 +        98: dout <= 108;
 +        99: dout <= 183;
 +        100: dout <= 8;
 +        101: dout <= 92;
 +        102: dout <= 44;
 +        103: dout <= 172;
 +        104: dout <= 21;
 +        105: dout <= 244;
 +        106: dout <= 6;
 +        107: dout <= 186;
 +        108: dout <= 5;
 +        109: dout <= 65;
 +        110: dout <= 208;
 +        111: dout <= 40;
 +        112: dout <= 47;
 +        113: dout <= 177;
 +        114: dout <= 98;
 +        115: dout <= 11;
 +        116: dout <= 253;
 +        117: dout <= 38;
 +        118: dout <= 9;
 +        119: dout <= 88;
 +        120: dout <= 157;
 +        121: dout <= 190;
 +        122: dout <= 28;
 +        123: dout <= 86;
 +        124: dout <= 7;
 +        125: dout <= 114;
 +        126: dout <= 196;
 +        127: dout <= 189;
 +        128: dout <= 230;
 +        129: dout <= 193;
 +        130: dout <= 220;
 +        131: dout <= 180;
 +        132: dout <= 121;
 +        133: dout <= 57;
 +        134: dout <= 169;
 +        135: dout <= 80;
 +        136: dout <= 26;
 +        137: dout <= 114;
 +        138: dout <= 223;
 +        139: dout <= 32;
 +        140: dout <= 149;
 +        141: dout <= 100;
 +        142: dout <= 131;
 +        143: dout <= 36;
 +        144: dout <= 245;
 +        145: dout <= 66;
 +        146: dout <= 155;
 +        147: dout <= 107;
 +        148: dout <= 4;
 +        149: dout <= 142;
 +        150: dout <= 35;
 +        151: dout <= 14;
 +        152: dout <= 8;
 +        153: dout <= 41;
 +        154: dout <= 24;
 +        155: dout <= 162;
 +        156: dout <= 130;
 +        157: dout <= 251;
 +        158: dout <= 239;
 +        159: dout <= 254;
 +        160: dout <= 59;
 +        161: dout <= 113;
 +        162: dout <= 64;
 +        163: dout <= 151;
 +        164: dout <= 159;
 +        165: dout <= 204;
 +        166: dout <= 181;
 +        167: dout <= 65;
 +        168: dout <= 108;
 +        169: dout <= 134;
 +        170: dout <= 1;
 +        171: dout <= 9;
 +        172: dout <= 104;
 +        173: dout <= 28;
 +        174: dout <= 185;
 +        175: dout <= 61;
 +        176: dout <= 25;
 +        177: dout <= 46;
 +        178: dout <= 59;
 +        179: dout <= 55;
 +        180: dout <= 133;
 +        181: dout <= 118;
 +        182: dout <= 79;
 +        183: dout <= 164;
 +        184: dout <= 54;
 +        185: dout <= 232;
 +        186: dout <= 246;
 +        187: dout <= 186;
 +        188: dout <= 111;
 +        189: dout <= 130;
 +        190: dout <= 148;
 +        191: dout <= 13;
 +        192: dout <= 107;
 +        193: dout <= 134;
 +        194: dout <= 46;
 +        195: dout <= 24;
 +        196: dout <= 205;
 +        197: dout <= 93;
 +        198: dout <= 132;
 +        199: dout <= 235;
 +        200: dout <= 156;
 +        201: dout <= 74;
 +        202: dout <= 251;
 +        203: dout <= 95;
 +        204: dout <= 4;
 +        205: dout <= 175;
 +        206: dout <= 25;
 +        207: dout <= 78;
 +        208: dout <= 215;
 +        209: dout <= 172;
 +        210: dout <= 4;
 +        211: dout <= 115;
 +        212: dout <= 105;
 +        213: dout <= 124;
 +        214: dout <= 53;
 +        215: dout <= 150;
 +        216: dout <= 18;
 +        217: dout <= 72;
 +        218: dout <= 95;
 +        219: dout <= 239;
 +        220: dout <= 19;
 +        221: dout <= 193;
 +        222: dout <= 49;
 +        223: dout <= 146;
 +        224: dout <= 100;
 +        225: dout <= 118;
 +        226: dout <= 192;
 +        227: dout <= 101;
 +        228: dout <= 31;
 +        229: dout <= 31;
 +        230: dout <= 20;
 +        231: dout <= 217;
 +        232: dout <= 164;
 +        233: dout <= 245;
 +        234: dout <= 177;
 +        235: dout <= 6;
 +        236: dout <= 168;
 +        237: dout <= 198;
 +        238: dout <= 185;
 +        239: dout <= 127;
 +        240: dout <= 91;
 +        241: dout <= 117;
 +        242: dout <= 204;
 +        243: dout <= 68;
 +        244: dout <= 134;
 +        245: dout <= 122;
 +        246: dout <= 244;
 +        247: dout <= 205;
 +        248: dout <= 238;
 +        249: dout <= 214;
 +        250: dout <= 75;
 +        251: dout <= 59;
 +        252: dout <= 125;
 +        253: dout <= 66;
 +        254: dout <= 109;
 +        default: dout <= 173;
 +    endcase
 +end
 +
 +endmodule
 +module rom3 (
 +    dout,
 +    addr,
 +    clk
 +);
 +
 +output [7:0] dout;
 +reg [7:0] dout;
 +input [7:0] addr;
 +input clk;
 +
 +
 +
 +always @(addr) begin: _rom3_RL
 +    reg [8-1:0] tmp;
 +    // synthesis parallel_case full_case
 +    case (addr)
 +        0: tmp = 244;
 +        1: tmp = 242;
 +        2: tmp = 14;
 +        3: tmp = 21;
 +        4: tmp = 213;
 +        5: tmp = 188;
 +        6: tmp = 171;
 +        7: tmp = 78;
 +        8: tmp = 155;
 +        9: tmp = 155;
 +        10: tmp = 148;
 +        11: tmp = 40;
 +        12: tmp = 110;
 +        13: tmp = 100;
 +        14: tmp = 185;
 +        15: tmp = 254;
 +        16: tmp = 243;
 +        17: tmp = 139;
 +        18: tmp = 113;
 +        19: tmp = 68;
 +        20: tmp = 9;
 +        21: tmp = 7;
 +        22: tmp = 119;
 +        23: tmp = 81;
 +        24: tmp = 97;
 +        25: tmp = 228;
 +        26: tmp = 134;
 +        27: tmp = 143;
 +        28: tmp = 60;
 +        29: tmp = 6;
 +        30: tmp = 83;
 +        31: tmp = 34;
 +        32: tmp = 130;
 +
 +        33: tmp = 255;
 +        34: tmp = 172;
 +        35: tmp = 46;
 +        36: tmp = 228;
 +        37: tmp = 203;
 +        38: tmp = 188;
 +        39: tmp = 232;
 +        40: tmp = 195;
 +        41: tmp = 202;
 +        42: tmp = 90;
 +        43: tmp = 251;
 +        44: tmp = 246;
 +        45: tmp = 41;
 +        46: tmp = 193;
 +        47: tmp = 183;
 +        48: tmp = 118;
 +        49: tmp = 135;
 +        50: tmp = 125;
 +        51: tmp = 236;
 +        52: tmp = 128;
 +        53: tmp = 212;
 +        54: tmp = 90;
 +        55: tmp = 226;
 +        56: tmp = 230;
 +        57: tmp = 118;
 +        58: tmp = 145;
 +        59: tmp = 235;
 +        60: tmp = 185;
 +        61: tmp = 124;
 +        62: tmp = 56;
 +        63: tmp = 83;
 +        64: tmp = 179;
 +        65: tmp = 42;
 +        66: tmp = 232;
 +        67: tmp = 68;
 +        68: tmp = 233;
 +        69: tmp = 79;
 +        70: tmp = 245;
 +        71: tmp = 180;
 +        72: tmp = 129;
 +        73: tmp = 132;
 +        74: tmp = 166;
 +        75: tmp = 150;
 +        76: tmp = 79;
 +        77: tmp = 53;
 +        78: tmp = 131;
 +        79: tmp = 239;
 +        80: tmp = 159;
 +        81: tmp = 19;
 +        82: tmp = 210;
 +        83: tmp = 185;
 +        84: tmp = 232;
 +        85: tmp = 48;
 +        86: tmp = 190;
 +        87: tmp = 15;
 +        88: tmp = 167;
 +        89: tmp = 69;
 +        90: tmp = 58;
 +        91: tmp = 224;
 +        92: tmp = 27;
 +        93: tmp = 133;
 +        94: tmp = 218;
 +        95: tmp = 62;
 +        96: tmp = 53;
 +        97: tmp = 225;
 +        98: tmp = 108;
 +        99: tmp = 183;
 +        100: tmp = 8;
 +        101: tmp = 92;
 +        102: tmp = 44;
 +        103: tmp = 172;
 +        104: tmp = 21;
 +        105: tmp = 244;
 +        106: tmp = 6;
 +        107: tmp = 186;
 +        108: tmp = 5;
 +        109: tmp = 65;
 +        110: tmp = 208;
 +        111: tmp = 40;
 +        112: tmp = 47;
 +        113: tmp = 177;
 +        114: tmp = 98;
 +        115: tmp = 11;
 +        116: tmp = 253;
 +        117: tmp = 38;
 +        118: tmp = 9;
 +        119: tmp = 88;
 +        120: tmp = 157;
 +        121: tmp = 190;
 +        122: tmp = 28;
 +        123: tmp = 86;
 +        124: tmp = 7;
 +        125: tmp = 114;
 +        126: tmp = 196;
 +        127: tmp = 189;
 +        128: tmp = 230;
 +        129: tmp = 193;
 +        130: tmp = 220;
 +        131: tmp = 180;
 +        132: tmp = 121;
 +        133: tmp = 57;
 +        134: tmp = 169;
 +        135: tmp = 80;
 +        136: tmp = 26;
 +        137: tmp = 114;
 +        138: tmp = 223;
 +        139: tmp = 32;
 +        140: tmp = 149;
 +        141: tmp = 100;
 +        142: tmp = 131;
 +        143: tmp = 36;
 +        144: tmp = 245;
 +        145: tmp = 66;
 +        146: tmp = 155;
 +        147: tmp = 107;
 +        148: tmp = 4;
 +        149: tmp = 142;
 +        150: tmp = 35;
 +        151: tmp = 14;
 +        152: tmp = 8;
 +
 +        153: tmp = 41;
 +        154: tmp = 24;
 +        155: tmp = 162;
 +        156: tmp = 130;
 +        157: tmp = 251;
 +        158: tmp = 239;
 +        159: tmp = 254;
 +        160: tmp = 59;
 +        161: tmp = 113;
 +        162: tmp = 64;
 +        163: tmp = 151;
 +        164: tmp = 159;
 +        165: tmp = 204;
 +        166: tmp = 181;
 +        167: tmp = 65;
 +        168: tmp = 108;
 +        169: tmp = 134;
 +        170: tmp = 1;
 +        171: tmp = 9;
 +        172: tmp = 104;
 +        173: tmp = 28;
 +        174: tmp = 185;
 +        175: tmp = 61;
 +        176: tmp = 25;
 +        177: tmp = 46;
 +        178: tmp = 59;
 +        179: tmp = 55;
 +        180: tmp = 133;
 +        181: tmp = 118;
 +        182: tmp = 79;
 +        183: tmp = 164;
 +        184: tmp = 54;
 +        185: tmp = 232;
 +        186: tmp = 246;
 +        187: tmp = 186;
 +        188: tmp = 111;
 +        189: tmp = 130;
 +        190: tmp = 148;
 +        191: tmp = 13;
 +        192: tmp = 107;
 +        193: tmp = 134;
 +        194: tmp = 46;
 +        195: tmp = 24;
 +        196: tmp = 205;
 +        197: tmp = 93;
 +        198: tmp = 132;
 +        199: tmp = 235;
 +        200: tmp = 156;
 +        201: tmp = 74;
 +        202: tmp = 251;
 +        203: tmp = 95;
 +        204: tmp = 4;
 +        205: tmp = 175;
 +        206: tmp = 25;
 +        207: tmp = 78;
 +        208: tmp = 215;
 +        209: tmp = 172;
 +        210: tmp = 4;
 +        211: tmp = 115;
 +        212: tmp = 105;
 +        213: tmp = 124;
 +        214: tmp = 53;
 +        215: tmp = 150;
 +        216: tmp = 18;
 +        217: tmp = 72;
 +        218: tmp = 95;
 +        219: tmp = 239;
 +        220: tmp = 19;
 +        221: tmp = 193;
 +        222: tmp = 49;
 +        223: tmp = 146;
 +        224: tmp = 100;
 +        225: tmp = 118;
 +        226: tmp = 192;
 +        227: tmp = 101;
 +        228: tmp = 31;
 +        229: tmp = 31;
 +        230: tmp = 20;
 +        231: tmp = 217;
 +        232: tmp = 164;
 +        233: tmp = 245;
 +        234: tmp = 177;
 +        235: tmp = 6;
 +        236: tmp = 168;
 +        237: tmp = 198;
 +        238: tmp = 185;
 +        239: tmp = 127;
 +        240: tmp = 91;
 +        241: tmp = 117;
 +        242: tmp = 204;
 +        243: tmp = 68;
 +        244: tmp = 134;
 +        245: tmp = 122;
 +        246: tmp = 244;
 +        247: tmp = 205;
 +        248: tmp = 238;
 +        249: tmp = 214;
 +        250: tmp = 75;
 +        251: tmp = 59;
 +        252: tmp = 125;
 +        253: tmp = 66;
 +        254: tmp = 109;
 +        default: tmp = 173;
 +    endcase
 +    dout <= tmp;
 +end
 +
 +endmodule
 +module shadowingSignal (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +module TaskCall (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +task _MYHDL214_ReturnFromTask;
 +    input [16-1:0] a;
 +    output [8-1:0] out;
 +    integer i;
 +begin: _MYHDL217_RETURN
 +    for (i=16-1; i>=0; i=i-1) begin
 +        if ((a[i] == 1)) begin
 +            out = i;
 +            disable _MYHDL217_RETURN;
 +        end
 +    end
 +    out = 23;
 +end
 +endtask
 +
 +always @(a) begin: _TaskCall
 +    reg [8-1:0] var;
 +    _MYHDL214_ReturnFromTask(a, var);
 +    out <= var;
 +end
 +
 +endmodule
 +module tb_adderDebug;
 +
 +reg [7:0] a;
 +reg [7:0] b;
 +wire [8:0] c;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b
 +    );
 +    $to_myhdl(
 +        c
 +    );
 +end
 +
 +adderDebug dut(
 +    a,
 +    b,
 +    c
 +);
 +
 +endmodule
 +module tb_adderRef;
 +
 +reg [7:0] a;
 +reg [7:0] b;
 +wire [8:0] c;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b
 +    );
 +    $to_myhdl(
 +        c
 +    );
 +end
 +
 +adderRef dut(
 +    a,
 +    b,
 +    c
 +);
 +
 +endmodule
 +module tb_augmOps;
 +
 +wire [7:0] Bitand;
 +wire [7:0] Bitor;
 +wire [7:0] Bitxor;
 +wire [7:0] FloorDiv;
 +wire [63:0] LeftShift;
 +wire [7:0] Mod;
 +wire [14:0] Mul;
 +wire [7:0] RightShift;
 +wire [7:0] Sub;
 +wire [8:0] Sum;
 +reg [7:0] left;
 +reg [6:0] right;
 +
 +initial begin
 +    $from_myhdl(
 +        left,
 +        right
 +    );
 +    $to_myhdl(
 +        Bitand,
 +        Bitor,
 +        Bitxor,
 +        FloorDiv,
 +        LeftShift,
 +        Mod,
 +
 +        Mul,
 +
 +        RightShift,
 +        Sub,
 +        Sum
 +    );
 +end
 +
 +augmOps dut(
 +    Bitand,
 +    Bitor,
 +    Bitxor,
 +    FloorDiv,
 +    LeftShift,
 +    Mod,
 +    Mul,
 +    RightShift,
 +    Sub,
 +
 +    Sum,
 +    left,
 +    right
 +);
 +
 +endmodule
 +module tb_behRef;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +behRef dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_bin2gray2;
 +
 +reg [7:0] B;
 +wire [7:0] G;
 +
 +initial begin
 +    $from_myhdl(
 +        B
 +    );
 +    $to_myhdl(
 +        G
 +    );
 +end
 +
 +bin2gray2 dut(
 +    B,
 +    G
 +);
 +
 +endmodule
 +module tb_bin2gray;
 +
 +reg [7:0] B;
 +wire [7:0] G;
 +
 +initial begin
 +    $from_myhdl(
 +        B
 +    );
 +    $to_myhdl(
 +        G
 +    );
 +end
 +
 +bin2gray dut(
 +    B,
 +    G
 +);
 +
 +endmodule
 +module tb_binaryOps;
 +
 +wire [7:0] Bitand;
 +wire [7:0] Bitor;
 +wire [7:0] Bitxor;
 +wire [7:0] FloorDiv;
 +wire [63:0] LeftShift;
 +wire [7:0] Mod;
 +wire [14:0] Mul;
 +wire [63:0] Pow;
 +wire [7:0] RightShift;
 +wire [7:0] Sub;
 +wire [8:0] Sum;
 +wire EQ;
 +wire NE;
 +wire LT;
 +wire GT;
 +wire LE;
 +wire GE;
 +
 +wire And;
 +wire Or;
 +reg [7:0] left;
 +reg [6:0] right;
 +
 +initial begin
 +    $from_myhdl(
 +        left,
 +        right
 +    );
 +    $to_myhdl(
 +        Bitand,
 +        Bitor,
 +        Bitxor,
 +        FloorDiv,
 +        LeftShift,
 +        Mod,
 +        Mul,
 +        Pow,
 +        RightShift,
 +        Sub,
 +        Sum,
 +        EQ,
 +        NE,
 +        LT,
 +        GT,
 +        LE,
 +        GE,
 +        And,
 +        Or
 +    );
 +end
 +
 +binaryOps dut(
 +    Bitand,
 +    Bitor,
 +    Bitxor,
 +    FloorDiv,
 +    LeftShift,
 +    Mod,
 +    Mul,
 +    Pow,
 +    RightShift,
 +    Sub,
 +    Sum,
 +    EQ,
 +    NE,
 +    LT,
 +    GT,
 +    LE,
 +    GE,
 +    And,
 +    Or,
 +    left,
 +    right
 +);
 +
 +endmodule
 +module tb_ConstWire2;
 +
 +reg p;
 +wire q;
 +
 +initial begin
 +    $from_myhdl(
 +        p
 +    );
 +    $to_myhdl(
 +        q
 +    );
 +end
 +
 +ConstWire2 dut(
 +    p,
 +    q
 +);
 +
 +endmodule
 +module tb_ConstWire3;
 +
 +reg [7:0] p;
 +wire [7:0] q;
 +
 +initial begin
 +    $from_myhdl(
 +        p
 +    );
 +    $to_myhdl(
 +        q
 +    );
 +end
 +
 +ConstWire3 dut(
 +    p,
 +    q
 +);
 +
 +endmodule
 +module tb_decRef;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +decRef dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_decTaskFreeVar;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +decTaskFreeVar dut(
 +    count,
 +
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_dec;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +dec dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_design1;
 +
 +reg a;
 +reg b;
 +reg c;
 +reg d;
 +wire p;
 +reg [7:0] q;
 +reg r;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b,
 +        c,
 +        d,
 +        q,
 +        r
 +    );
 +    $to_myhdl(
 +        p
 +    );
 +end
 +
 +design1 dut(
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +endmodule
 +module tb_design2;
 +
 +reg a;
 +reg b;
 +reg c;
 +reg d;
 +wire p;
 +wire [7:0] q;
 +wire r;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b,
 +        c,
 +        d
 +    );
 +    $to_myhdl(
 +        p,
 +        q,
 +        r
 +    );
 +end
 +
 +design2 dut(
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +endmodule
 +module tb_design3;
 +
 +reg a;
 +reg b;
 +reg c;
 +reg d;
 +wire p;
 +wire [7:0] q;
 +wire r;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b,
 +        c,
 +        d
 +    );
 +    $to_myhdl(
 +        p,
 +        q,
 +        r
 +    );
 +end
 +
 +design3 dut(
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +endmodule
 +module tb_design4;
 +
 +reg a;
 +reg b;
 +reg c;
 +reg d;
 +wire p;
 +wire [7:0] q;
 +wire r;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b,
 +        c,
 +        d
 +    );
 +    $to_myhdl(
 +        p,
 +        q,
 +        r
 +    );
 +end
 +
 +design4 dut(
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +endmodule
 +module tb_design5;
 +
 +reg a;
 +reg b;
 +reg c;
 +reg d;
 +wire p;
 +wire [7:0] q;
 +wire r;
 +
 +initial begin
 +    $from_myhdl(
 +        a,
 +        b,
 +        c,
 +        d
 +    );
 +    $to_myhdl(
 +        p,
 +        q,
 +        r
 +    );
 +end
 +
 +design5 dut(
 +    a,
 +    b,
 +    c,
 +    d,
 +    p,
 +    q,
 +    r
 +);
 +
 +endmodule
 +module tb_ForBreakContinueLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForBreakContinueLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForBreakLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForBreakLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForContinueLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForContinueLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForLoop1;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForLoop1 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForLoop2;
 +
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForLoop2 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForLoop3;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForLoop3 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForLoop4;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForLoop4 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForLoop5;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForLoop5 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ForLoop6;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +ForLoop6 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_FramerCtrl_alt;
 +
 +wire SOF;
 +wire [2:0] state;
 +reg syncFlag;
 +reg clk;
 +reg reset_n;
 +
 +initial begin
 +    $from_myhdl(
 +        syncFlag,
 +        clk,
 +        reset_n
 +    );
 +    $to_myhdl(
 +        SOF,
 +        state
 +    );
 +end
 +
 +FramerCtrl_alt dut(
 +    SOF,
 +    state,
 +    syncFlag,
 +    clk,
 +    reset_n
 +);
 +
 +endmodule
 +module tb_FramerCtrl_ref;
 +
 +wire SOF;
 +wire [2:0] state;
 +reg syncFlag;
 +reg clk;
 +reg reset_n;
 +
 +initial begin
 +    $from_myhdl(
 +        syncFlag,
 +        clk,
 +        reset_n
 +    );
 +    $to_myhdl(
 +        SOF,
 +        state
 +    );
 +end
 +
 +FramerCtrl_ref dut(
 +    SOF,
 +    state,
 +    syncFlag,
 +    clk,
 +    reset_n
 +);
 +
 +endmodule
 +module tb_FramerCtrl;
 +
 +wire SOF;
 +wire [2:0] state;
 +reg syncFlag;
 +reg clk;
 +reg reset_n;
 +
 +initial begin
 +    $from_myhdl(
 +        syncFlag,
 +        clk,
 +        reset_n
 +    );
 +    $to_myhdl(
 +        SOF,
 +        state
 +    );
 +end
 +
 +FramerCtrl dut(
 +    SOF,
 +    state,
 +    syncFlag,
 +    clk,
 +    reset_n
 +);
 +
 +endmodule
 +module tb_FunctionCall;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +FunctionCall dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_GrayIncReg;
 +
 +wire [7:0] graycnt;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        graycnt
 +    );
 +end
 +
 +GrayIncReg dut(
 +    graycnt,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_HecCalculatorFunc;
 +
 +wire [7:0] hec;
 +reg [31:0] header;
 +
 +initial begin
 +    $from_myhdl(
 +        header
 +    );
 +    $to_myhdl(
 +
 +        hec
 +    );
 +end
 +
 +HecCalculatorFunc dut(
 +    hec,
 +    header
 +);
 +
 +endmodule
 +module tb_HecCalculatorPlain;
 +
 +wire [7:0] hec;
 +reg [31:0] header;
 +
 +initial begin
 +    $from_myhdl(
 +        header
 +    );
 +    $to_myhdl(
 +        hec
 +    );
 +end
 +
 +HecCalculatorPlain dut(
 +    hec,
 +    header
 +);
 +
 +endmodule
 +module tb_HecCalculatorTask2;
 +
 +wire [7:0] hec;
 +reg [31:0] header;
 +
 +initial begin
 +    $from_myhdl(
 +        header
 +    );
 +    $to_myhdl(
 +        hec
 +    );
 +end
 +
 +HecCalculatorTask2 dut(
 +    hec,
 +    header
 +);
 +
 +endmodule
 +module tb_HecCalculatorTask;
 +
 +wire [7:0] hec;
 +reg [31:0] header;
 +
 +initial begin
 +    $from_myhdl(
 +        header
 +    );
 +    $to_myhdl(
 +        hec
 +    );
 +end
 +
 +HecCalculatorTask dut(
 +    hec,
 +    header
 +);
 +
 +endmodule
 +module tb_incRef;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +incRef dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_incTaskFreeVar;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +incTaskFreeVar dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_incTask;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +incTask dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_inc;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +inc dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_Infer1;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +Infer1 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_Infer2;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +Infer2 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_Infer3;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +Infer3 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_Infer4;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +Infer4 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_Infer5;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +Infer5 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_InferError7;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +InferError7 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_multiOps;
 +
 +wire [6:0] Bitand;
 +wire [6:0] Bitor;
 +wire [6:0] Bitxor;
 +wire And;
 +wire Or;
 +reg [2:0] argm;
 +reg [6:0] argn;
 +reg [3:0] argp;
 +
 +initial begin
 +    $from_myhdl(
 +        argm,
 +        argn,
 +        argp
 +    );
 +    $to_myhdl(
 +        Bitand,
 +        Bitor,
 +        Bitxor,
 +        And,
 +        Or
 +    );
 +end
 +
 +multiOps dut(
 +    Bitand,
 +    Bitor,
 +    Bitxor,
 +    And,
 +    Or,
 +    argm,
 +    argn,
 +    argp
 +);
 +
 +endmodule
 +module tb_my_bundle;
 +
 +reg p;
 +wire q;
 +
 +initial begin
 +    $from_myhdl(
 +        p
 +    );
 +    $to_myhdl(
 +        q
 +    );
 +end
 +
 +my_bundle dut(
 +    p,
 +    q
 +);
 +
 +endmodule
 +module tb_NestedForLoop1;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +NestedForLoop1 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_NestedForLoop2;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +NestedForLoop2 dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_ram2;
 +
 +wire [7:0] dout;
 +reg [7:0] din;
 +reg [7:0] addr;
 +reg we;
 +reg clk;
 +
 +initial begin
 +    $from_myhdl(
 +        din,
 +        addr,
 +        we,
 +        clk
 +    );
 +    $to_myhdl(
 +        dout
 +    );
 +end
 +
 +ram2 dut(
 +    dout,
 +    din,
 +    addr,
 +    we,
 +    clk
 +);
 +
 +endmodule
 +module tb_ram3;
 +
 +wire [7:0] dout;
 +reg [7:0] din;
 +reg [7:0] addr;
 +reg we;
 +reg clk;
 +
 +initial begin
 +    $from_myhdl(
 +        din,
 +        addr,
 +
 +        we,
 +        clk
 +    );
 +    $to_myhdl(
 +        dout
 +    );
 +end
 +
 +ram3 dut(
 +    dout,
 +    din,
 +    addr,
 +    we,
 +    clk
 +);
 +
 +endmodule
 +module tb_ram;
 +
 +wire [7:0] dout;
 +reg [7:0] din;
 +reg [7:0] addr;
 +reg we;
 +reg clk;
 +
 +initial begin
 +    $from_myhdl(
 +        din,
 +        addr,
 +        we,
 +        clk
 +    );
 +    $to_myhdl(
 +        dout
 +    );
 +end
 +
 +ram dut(
 +    dout,
 +    din,
 +    addr,
 +    we,
 +    clk
 +);
 +
 +endmodule
 +module tb_RandomScrambler;
 +
 +wire o7;
 +wire o6;
 +wire o5;
 +wire o4;
 +wire o3;
 +wire o2;
 +wire o1;
 +wire o0;
 +reg i7;
 +reg i6;
 +reg i5;
 +reg i4;
 +reg i3;
 +reg i2;
 +reg i1;
 +reg i0;
 +
 +initial begin
 +    $from_myhdl(
 +        i7,
 +        i6,
 +        i5,
 +        i4,
 +        i3,
 +        i2,
 +        i1,
 +        i0
 +    );
 +    $to_myhdl(
 +        o7,
 +        o6,
 +        o5,
 +        o4,
 +        o3,
 +        o2,
 +        o1,
 +        o0
 +    );
 +end
 +
 +RandomScrambler dut(
 +    o7,
 +    o6,
 +    o5,
 +    o4,
 +    o3,
 +    o2,
 +    o1,
 +    o0,
 +    i7,
 +    i6,
 +    i5,
 +    i4,
 +    i3,
 +    i2,
 +    i1,
 +    i0
 +);
 +
 +endmodule
 +module tb_rom1;
 +
 +wire [7:0] dout;
 +reg [7:0] addr;
 +reg clk;
 +
 +initial begin
 +    $from_myhdl(
 +        addr,
 +
 +        clk
 +    );
 +    $to_myhdl(
 +        dout
 +    );
 +end
 +
 +rom1 dut(
 +    dout,
 +    addr,
 +    clk
 +);
 +
 +endmodule
 +module tb_rom2;
 +
 +wire [7:0] dout;
 +reg [7:0] addr;
 +reg clk;
 +
 +initial begin
 +    $from_myhdl(
 +        addr,
 +        clk
 +    );
 +    $to_myhdl(
 +        dout
 +    );
 +end
 +
 +rom2 dut(
 +    dout,
 +    addr,
 +    clk
 +);
 +
 +endmodule
 +module tb_rom3;
 +
 +wire [7:0] dout;
 +reg [7:0] addr;
 +reg clk;
 +
 +initial begin
 +    $from_myhdl(
 +        addr,
 +        clk
 +    );
 +    $to_myhdl(
 +        dout
 +    );
 +end
 +
 +rom3 dut(
 +    dout,
 +    addr,
 +    clk
 +);
 +
 +endmodule
 +module tb_TaskCall;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +TaskCall dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_top;
 +
 +wire [7:0] count;
 +reg enable;
 +reg clock;
 +reg reset;
 +
 +initial begin
 +    $from_myhdl(
 +        enable,
 +        clock,
 +        reset
 +    );
 +    $to_myhdl(
 +        count
 +    );
 +end
 +
 +top dut(
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +endmodule
 +module tb_unaryOps;
 +
 +wire Not;
 +wire [6:0] Invert;
 +wire [6:0] UnaryAdd;
 +wire [6:0] UnarySub;
 +reg [6:0] arg;
 +
 +initial begin
 +    $from_myhdl(
 +        arg
 +    );
 +    $to_myhdl(
 +        Not,
 +        Invert,
 +        UnaryAdd,
 +        UnarySub
 +    );
 +end
 +
 +unaryOps dut(
 +    Not,
 +    Invert,
 +    UnaryAdd,
 +    UnarySub,
 +    arg
 +);
 +
 +endmodule
 +module tb_WhileBreakContinueLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +WhileBreakContinueLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_WhileBreakLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +WhileBreakLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_WhileContinueLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +WhileContinueLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module tb_WhileLoop;
 +
 +reg [15:0] a;
 +wire [15:0] out;
 +
 +initial begin
 +    $from_myhdl(
 +        a
 +    );
 +    $to_myhdl(
 +        out
 +    );
 +end
 +
 +WhileLoop dut(
 +    a,
 +    out
 +);
 +
 +endmodule
 +module top (
 +    count,
 +    enable,
 +    clock,
 +    reset
 +);
 +
 +output [7:0] count;
 +reg [7:0] count;
 +input enable;
 +input clock;
 +input reset;
 +
 +
 +
 +initial begin: _top_inc_initial_inst
 +    integer i;
 +    for (i=0; i<100; i=i+1) begin
 +        @ (posedge clock or negedge reset);
 +        if ((reset == 0)) begin
 +            count <= 0;
 +        end
 +        else begin
 +            if (enable) begin
 +                count <= ((count + 1) % 256);
 +            end
 +        end
 +    end
 +    $display("StopSimulation");
 +    $finish;
 +end
 +
 +
 +endmodule
 +module unaryOps (
 +    Not,
 +    Invert,
 +    UnaryAdd,
 +    UnarySub,
 +    arg
 +);
 +
 +output Not;
 +reg Not;
 +output [6:0] Invert;
 +reg [6:0] Invert;
 +output [6:0] UnaryAdd;
 +reg [6:0] UnaryAdd;
 +output [6:0] UnarySub;
 +reg [6:0] UnarySub;
 +input [6:0] arg;
 +
 +
 +
 +always @(arg) begin: _unaryOps
 +    Not <= (!arg);
 +    Invert <= (~arg);
 +    UnaryAdd <= (+arg);
 +    UnarySub <= (-(-arg));
 +end
 +
 +endmodule
 +module WhileBreakContinueLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _WhileBreakContinueLoop
 +    integer var;
 +    integer i;
 +    var = 0;
 +    i = (16 - 1);
 +    out <= 0;
 +    begin: _MYHDL221_BREAK
 +    while ((i >= 0)) begin: _MYHDL222_LOOP
 +        if ((a[i] == 0)) begin
 +            i = i - 1;
 +            disable _MYHDL222_LOOP;
 +        end
 +        out <= i;
 +        disable _MYHDL221_BREAK;
 +    end
 +    end
 +end
 +
 +endmodule
 +module WhileBreakLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _WhileBreakLoop
 +    integer var;
 +    integer i;
 +    var = 0;
 +    i = (16 - 1);
 +    out <= 0;
 +    begin: _MYHDL226_BREAK
 +    while ((i >= 0)) begin
 +        if ((a[i] == 1)) begin
 +            out <= i;
 +            disable _MYHDL226_BREAK;
 +        end
 +        i = i - 1;
 +    end
 +    end
 +end
 +
 +endmodule
 +module WhileContinueLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _WhileContinueLoop
 +    integer var;
 +    integer i;
 +    var = 0;
 +    i = (16 - 1);
 +    while ((i >= 0)) begin: _MYHDL232_LOOP
 +        if ((a[i] == 0)) begin
 +            i = i - 1;
 +            disable _MYHDL232_LOOP;
 +        end
 +        var = var + 1;
 +        i = i - 1;
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +module WhileLoop (
 +    a,
 +    out
 +);
 +
 +input [15:0] a;
 +output [15:0] out;
 +reg [15:0] out;
 +
 +
 +
 +always @(a) begin: _WhileLoop
 +    integer var;
 +    integer i;
 +    var = 0;
 +    i = (16 - 1);
 +    while ((i >= 0)) begin
 +        if ((a[i] == 1)) begin
 +            var = var + 1;
 +        end
 +        i = i - 1;
 +    end
 +    out <= var;
 +end
 +
 +endmodule
 +
 +
 +
 +
 +</code>
verilog.txt ยท Last modified: 2009/03/28 09:42 (external edit)
 
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