What I am working on

Last update: April 2013


I am working as a consultant with a focus on electronic design. For an overview of my services, see Consultancy Services. On this page, I will describe my current activities.


I am the creator and maintainer of MyHDL, an open-source package that turns Python into a hardware description language.

Many things in HDL-based design are not the way I think they ought to be. I have complained a lot about this in the past. MyHDL is my attempt to turn that negative energy into something positive. Instead of complaining, I now implement it the way I want!

I am happy to see that more and more people find MyHDL useful. There is now working silicon designed with MyHDL, and I intend to build further on that momentum.


Sigasi is a young company that develops a next-generation VHDL design environment. I am advising them both on business development and technical matters.

Sigasi’s founders have a lot of experience with modern integrated development environments such as Eclipse. Their idea is to develop a similar tool for VHDL-based hardware development. I must say this opened a new world to me, and I’m now convinced this is the way forward for HDL-based design.

The differentiating technology behind Sigasi HDT is that it contains an ultra-fast VHDL parser and analyzer. This means that at any given moment during development, the tool understands your project as a VHDL design instead of a bunch of files. This means that any development task can be enhanced with design intelligence, which can boost productivity tremendously.

For example, consider navigation. By simply hovering over an identifier, you get instant feedback about its declaration and you can jump to it immediately.

Another example is error reporting. You don’t just get feedback about syntax errors, but also about conceptual problems such as incomplete sensitivity lists or missing signal declarations. Moreover, the tool can automatically fix such errors.

One more example is autocompletion. Of course, traditional template-based methods are available, but the tool goes much further using its knowledge of the design. For example, when you start typing an instantiation, it can let you choose between all matching entities, and fill in the port map automatically.

The flagship functionality is automated refactoring, which is a modern software technique to improve code by restructuring it without modifying functionality. The simplest (but incredibly useful) example is Rename, which is not based on string equality within one file, but on object identify in the whole design. Refactorings can be very sophisticated, for example allowing you to modify the hierarchical structure of the design automatically.

In short, if you are designing in VHDL, I strongly advise you to take a look at Sigasi!


Easics offers digital design services with a strong focus on methodology.

I co-founded Easics back in 1992. After a take-over in 2000 and a management buy-out in 2004, Easics is now owned and managed by two former employees that I respect very much. I still consider it my baby. Over the years, the spirit has remained intact, which is that “methodology counts”. I am a director with Easics and occasionally I do technical work for them.

Easics has an outstanding track record of design successes, something which I am very proud of. Of course, over the years the focus has shifted. Today we are very strong in hardware-software co-design. Also, there is a clear trend away from digital ASICs to complex FPGAs. At the same time, the value in ASICs is clearly moving towards mixed-signal designs. Easics is specializing in such designs, in a strong partnership with the analog design firm ICsense.

If you need digital or mixed-signal design expertise, consider Easics. You won’t be disappointed.